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install *_nowide.lut files
[yosys.git]
/
techlibs
/
xilinx
/
abc_xc7.box
2019-06-28
Eddie Hung
Merge pull request #1098 from YosysHQ/xaig
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2019-06-27
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-06-27
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-06-27
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-06-27
Eddie Hung
Update comment on boxes
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2019-06-26
Eddie Hung
Merge branch 'koriakin/xc7nocarrymux' into xaig
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2019-06-26
Eddie Hung
Merge branch 'koriakin/xc7nocarrymux' into xaig
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2019-06-26
Eddie Hung
Merge branch 'koriakin/xc7nocarrymux' into xaig
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2019-06-26
Eddie Hung
Merge branch 'koriakin/xc7nocarrymux' into xaig
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2019-06-25
Eddie Hung
Realistic delays for RAM32X1D too
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2019-06-25
Eddie Hung
Add RAM32X1D box info
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2019-06-25
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-06-25
Eddie Hung
Use LUT delays for dist RAM delays
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2019-06-25
Eddie Hung
Add Xilinx dist RAM as comb boxes
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2019-06-25
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-06-22
Eddie Hung
Add comment to xc7 box
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2019-06-22
Eddie Hung
Carry in/out box ordering now move to end, not swap...
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2019-06-22
Eddie Hung
Remove DFF and RAMD box info for now
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2019-06-22
Eddie Hung
Merge branch 'master' into xaig
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2019-06-22
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-06-21
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-06-14
Eddie Hung
As per @daveshah1 remove async DFF timing from xilinx
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2019-06-14
Eddie Hung
Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}
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