git.libre-soc.org Git - yosys.git/history - techlibs/xilinx/brams

2019-03-04	Keith Rothman	Revert BRAM WRITE_MODE changes.	blob \| commitdiff \| raw
2019-03-01	Keith Rothman	Changes required for VPR place and route synth_xilinx.	blob \| commitdiff \| raw \| diff to current
2016-07-08	Clifford Wolf	Merge branch 'yosys-0.5-vtr' of https://github.com...	blob \| commitdiff \| raw
2015-12-07	Clifford Wolf	Merge pull request #108 from cseed/master	blob \| commitdiff \| raw
2015-09-25	Clifford Wolf	Added read-enable to memory model	blob \| commitdiff \| raw
2015-04-06	Clifford Wolf	Added support for initialized xilinx brams	blob \| commitdiff \| raw \| diff to current
2015-04-03	Ahmed Irfan	Merge branch 'master' of https://github.com/cliffordwol...	blob \| commitdiff \| raw \| diff to current
2015-02-01	Clifford Wolf	Added missing ports and parameters to xilinx brams	blob \| commitdiff \| raw \| diff to current
2015-01-18	Clifford Wolf	Merge branch 'master' of github.com:cliffordwolf/yosys	blob \| commitdiff \| raw \| diff to current
2015-01-18	Clifford Wolf	Various cleanups in xilinx techlib	blob \| commitdiff \| raw \| diff to current