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Try new LUT delays
[yosys.git]
/
techlibs
/
xilinx
/
cells_map.v
2019-05-23
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-05-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/opt_rmdff...
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2019-05-22
Eddie Hung
Fix/workaround symptom unveiled by #1023
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2019-05-21
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-05-21
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-05-06
Clifford Wolf
Merge pull request #871 from YosysHQ/verific_import
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2019-05-06
Clifford Wolf
Merge branch 'master' of github.com:YosysHQ/yosys into...
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2019-05-03
Eddie Hung
Merge remote-tracking branch 'origin/master' into cliff...
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2019-05-03
Eddie Hung
Rename cells_map.v to prevent clash with ff_map.v
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2019-05-03
Clifford Wolf
Merge pull request #969 from YosysHQ/clifford/pmgenstuff
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2019-05-03
Clifford Wolf
Merge pull request #976 from YosysHQ/clifford/fix974
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2019-05-02
Eddie Hung
Trim off leading 1'bx in A
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2019-05-02
Eddie Hung
Add don't care optimisation
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2019-05-02
Eddie Hung
Merge remote-tracking branch 'origin/clifford/pmgenstuf...
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2019-05-02
Eddie Hung
Revert to pre-muxcover approach
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2019-05-02
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-05-02
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-05-02
Clifford Wolf
Merge pull request #963 from YosysHQ/eddie/synth_xilinx...
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2019-05-02
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-04-30
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-04-30
Benedikt Tutzer
Merge branch 'master' of https://github.com/YosysHQ...
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2019-04-28
Eddie Hung
Move neg-pol to pos-pol mapping from ff_map to cells_map.v
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2019-04-27
Eddie Hung
Fix spacing
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2019-04-26
Eddie Hung
Try a different approach with 'muxcover'
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2019-04-26
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-04-26
Eddie Hung
Cleanup superseded
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2019-04-26
Eddie Hung
Merge remote-tracking branch 'origin/eddie/split_shiftx...
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2019-04-26
Eddie Hung
Merge branch 'eddie/split_shiftx' into xc7mux
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2019-04-23
Eddie Hung
Tweak
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2019-04-23
Eddie Hung
Fix for A_WIDTH == 2 but B_WIDTH==3
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2019-04-23
Eddie Hung
Trim A_WIDTH by Y_WIDTH-1
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2019-04-22
Eddie Hung
Add comment
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2019-04-22
Eddie Hung
Fix for mux_case_* mappings
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2019-04-22
Eddie Hung
Fix for non-pow2 width muxes
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2019-04-22
Eddie Hung
Merge pull request #914 from YosysHQ/xc7srl
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2019-04-22
Eddie Hung
Add synth_xilinx -nomux option
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2019-04-22
Eddie Hung
Merge branch 'xaig' into xc7mux
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2019-04-22
Eddie Hung
Merge remote-tracking branch 'origin/xc7srl' into xc7mux
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2019-04-22
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-04-21
Eddie Hung
Merge branch 'map_cells_before_map_luts' into xc7srl
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2019-04-21
Eddie Hung
Merge remote-tracking branch 'origin/clifford/pmux2shif...
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2019-04-21
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-04-20
Eddie Hung
Merge remote-tracking branch 'origin/pmux2shiftx' into...
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2019-04-20
Eddie Hung
Merge remote-tracking branch 'origin' into xc7srl
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2019-04-16
Eddie Hung
Merge branch 'xaig' into xc7mux
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2019-04-16
Eddie Hung
Merge branch 'xaig' into xc7mux
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2019-04-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-04-11
Eddie Hung
Merge remote-tracking branch 'origin/pmux2shiftx' into...
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2019-04-11
Eddie Hung
Merge remote-tracking branch 'origin/pmux2shiftx' into...
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2019-04-11
Eddie Hung
Fix cells_map.v some more
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2019-04-11
Eddie Hung
More fine tuning
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2019-04-11
Eddie Hung
Fix cells_map.v
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2019-04-11
Eddie Hung
Fix typo
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2019-04-11
Eddie Hung
Juggle opt calls in synth_xilinx
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2019-04-11
Eddie Hung
Merge branch 'xaig' into xc7mux
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2019-04-11
Eddie Hung
WIP for cells_map.v -- maybe working?
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2019-04-10
Eddie Hung
Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1
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2019-04-10
Eddie Hung
Fix for when B_SIGNED = 1
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2019-04-10
Eddie Hung
Merge branch 'xaig' into xc7mux
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2019-04-10
Eddie Hung
Tidy up
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2019-04-10
Eddie Hung
WIP for $shiftx to wide mux
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2019-04-08
Eddie Hung
Merge branch 'master' into xaig
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2019-04-08
Eddie Hung
Merge branch 'undo_pr895' into xc7srl
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2019-04-06
Eddie Hung
Call shregmap twice -- once for variable, another for...
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2019-04-05
Eddie Hung
Merge branch 'eddie/fix_retime' into xc7srl
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2019-04-05
Eddie Hung
Merge branch 'eddie/fix_retime' into xc7srl
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2019-04-05
Eddie Hung
techmap inside map_cells stage
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2019-04-04
Eddie Hung
Merge branch 'map_cells_before_map_luts' into xc7srl
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2019-04-04
Eddie Hung
Use soft-logic, not LUT3 instantiation
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2019-04-04
Eddie Hung
Merge branch 'map_cells_before_map_luts' into xc7srl
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2019-04-04
Eddie Hung
Cleanup comments
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2019-04-03
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-04-01
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-03-28
Benedikt Tutzer
Merge remote-tracking branch 'origin/master' into featu...
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2019-03-25
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-22
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-20
Eddie Hung
Fine tune cells_map.v
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2019-03-20
Eddie Hung
Revert $__SHREG_ to orig; use $__XILINX_SHREG for varia...
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2019-03-20
Eddie Hung
Add support for variable length Xilinx SRL > 128
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2019-03-19
Eddie Hung
Fix spacing
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2019-03-19
Eddie Hung
Fix INIT for variable length SRs that have been bumped...
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2019-03-19
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-19
Eddie Hung
Merge https://github.com/YosysHQ/yosys into read_aiger
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2019-03-16
Eddie Hung
Only accept <128 for variable length, only if $shiftx...
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2019-03-16
Eddie Hung
Cleanup synth_xilinx
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2019-03-16
Eddie Hung
Working
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2019-03-14
Eddie Hung
Reverse bits in INIT parameter for Xilinx, since MSB...
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2019-03-14
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-14
Eddie Hung
Fix cells_map for SRL
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2019-03-13
Eddie Hung
Refactor $__SHREG__ in cells_map.v
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2019-03-09
Clifford Wolf
Merge pull request #859 from smunaut/ice40_braminit
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2019-03-05
Clifford Wolf
Merge pull request #842 from litghost/merge_upstream
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2019-03-01
Keith Rothman
Changes required for VPR place and route synth_xilinx.
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2019-02-28
Eddie Hung
Fix SRL16/32 techmap off-by-one
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2019-02-28
Eddie Hung
synth_xilinx to call shregmap with enable support
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2019-02-28
Eddie Hung
synth_xilinx to use shregmap with -params too
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2019-02-28
Eddie Hung
Add techmap rule for $__SHREG_DFF_P_ to SRL16/32
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2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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2018-08-15
Clifford Wolf
Merge pull request #513 from udif/pr_reg_wire_error
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2018-05-04
Clifford Wolf
Merge pull request #537 from mithro/yosys-vpr
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