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FDCE ports to be alphabetical
[yosys.git]
/
techlibs
/
xilinx
/
cells_sim.v
2019-12-31
Eddie Hung
FDCE ports to be alphabetical
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2019-12-30
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-12-28
Miodrag Milanovic
Merge remote-tracking branch 'origin/master' into iopad...
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2019-12-25
Marcin Kościelnicki
Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen
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2019-12-23
Marcin Kościelnicki
xilinx: Test our DSP48A/DSP48A1 simulation models.
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2019-12-20
Eddie Hung
Merge pull request #1588 from YosysHQ/eddie/xaiger_cleanup
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2019-12-20
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-12-20
Eddie Hung
Add abc9_arrival times for RAM{32,64}M
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2019-12-20
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-12-20
Eddie Hung
Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lut
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2019-12-19
Eddie Hung
Split into $__ABC9_ASYNC[01], do not add cell->type...
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2019-12-19
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-12-19
Eddie Hung
Merge pull request #1581 from YosysHQ/clifford/fix1565
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2019-12-19
Eddie Hung
Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
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2019-12-19
Eddie Hung
Merge pull request #1569 from YosysHQ/eddie/fix_1531
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2019-12-19
Eddie Hung
Merge pull request #1571 from YosysHQ/eddie/fix_1570
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2019-12-19
Marcin Kościelnicki
xilinx: Add simulation models for remaining CLB primitives.
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2019-12-18
Eddie Hung
Merge branch 'master' of github.com:YosysHQ/yosys
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2019-12-18
David Shah
Merge pull request #1563 from YosysHQ/dave/async-prld
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2019-12-18
Eddie Hung
Merge pull request #1572 from nakengelhardt/scratchpad_pass
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2019-12-18
Marcin Kościelnicki
xilinx: Add xilinx_dffopt pass (#1557)
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2019-12-17
Eddie Hung
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram
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2019-12-16
Eddie Hung
Merge pull request #1577 from gromero/for-yosys
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2019-12-13
Eddie Hung
RAM64M8 to also have [5:0] for address
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2019-12-13
Eddie Hung
Fix RAM64M model to have 6 bit address bus
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2019-12-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-12-12
Diego H
Merge https://github.com/YosysHQ/yosys into bram_xilinx
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2019-12-10
Eddie Hung
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapc...
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2019-12-07
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-12-05
Clifford Wolf
Merge pull request #1551 from whitequark/manual-cell...
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2019-12-05
Eddie Hung
Oh deary me
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2019-12-04
Marcin Kościelnicki
xilinx: Add models for LUTRAM cells. (#1537)
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2019-12-03
Clifford Wolf
Merge pull request #1524 from pepijndevos/gowindffinit
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2019-11-28
Eddie Hung
Merge remote-tracking branch 'origin/eddie/submod_po...
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2019-11-27
Eddie Hung
Merge remote-tracking branch 'origin/eddie/submod_po...
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2019-11-27
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-11-27
Eddie Hung
Merge remote-tracking branch 'origin/eddie/submod_po...
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2019-11-27
Clifford Wolf
Merge pull request #1501 from YosysHQ/dave/mem_copy_attr
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2019-11-27
Eddie Hung
Merge remote-tracking branch 'origin/eddie/write_xaiger...
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2019-11-27
Eddie Hung
Merge remote-tracking branch 'origin/eddie/clkpart...
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2019-11-27
Eddie Hung
Merge remote-tracking branch 'origin/eddie/submod_po...
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2019-11-27
Eddie Hung
Merge branch 'master' into xaig_dff
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2019-11-26
Marcin Kościelnicki
xilinx: Add simulation models for IOBUF and OBUFT.
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2019-11-25
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-11-25
Marcin Kościelnicki
clkbufmap: Add support for inverters in clock path.
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2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/clkpart...
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2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/clkpart...
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2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/clkpart...
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2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/clkpart...
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2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/submod_po...
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2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/submod_po...
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2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/submod_po...
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2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/clkpart...
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2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/submod_po...
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2019-11-22
Eddie Hung
Merge branch 'eddie/clkpart' into xaig_dff
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2019-11-22
Eddie Hung
Merge branch 'eddie/clkpart' into xaig_dff
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2019-11-22
Eddie Hung
Merge branch 'master' of github.com:YosysHQ/yosys
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2019-11-19
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-11-19
Clifford Wolf
Merge pull request #1449 from pepijndevos/gowin
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2019-11-19
Marcin Kościelnicki
xilinx: Add simulation models for MULT18X18* and DSP48A*.
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2019-10-27
Clifford Wolf
Merge pull request #1393 from whitequark/write_verilog...
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2019-10-21
Pepijn de Vos
Merge branch 'master' of https://github.com/YosysHQ...
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2019-10-18
Miodrag Milanović
Merge branch 'master' into mmicko/efinix
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2019-10-18
Miodrag Milanović
Merge branch 'master' into mmicko/anlogic
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2019-10-18
Miodrag Milanović
Merge branch 'master' into eddie/pr1352
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2019-10-15
Benedikt Tutzer
Merge branch 'master' of https://github.com/YosysHQ...
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2019-10-14
Clifford Wolf
Use "(id)" instead of "id" for types as temporary hack
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2019-10-10
Miodrag Milanović
Merge pull request #1445 from YosysHQ/mwk/xilinx_ibufg
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2019-10-10
Marcin Kościelnicki
xilinx: Add simulation model for IBUFG.
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2019-10-08
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-10-08
Eddie Hung
Merge pull request #1432 from YosysHQ/eddie/fix1427
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2019-10-08
Eddie Hung
Merge pull request #1433 from YosysHQ/eddie/equiv_opt_a...
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2019-10-08
Eddie Hung
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
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2019-10-06
Eddie Hung
Do not require changes to cells_sim.v; try and work...
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2019-10-05
Eddie Hung
Merge branch 'master' into eddie/abc_to_abc9
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2019-10-05
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-10-04
Eddie Hung
Merge remote-tracking branch 'origin/eddie/abc_to_abc9...
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2019-10-04
Eddie Hung
Rename abc_* names/attributes to more precisely be...
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2019-10-03
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-10-01
Eddie Hung
More fixes
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2019-10-01
Eddie Hung
Escape Verilog identifiers for legality outside of...
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2019-10-01
Sergey
Merge branch 'master' into SergeyDegtyar/efinix
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2019-10-01
Sergey
Merge branch 'master' into SergeyDegtyar/anlogic
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2019-09-30
Eddie Hung
Remove need for $currQ port connection
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2019-09-30
Eddie Hung
Merge branch 'SergeyDegtyar/ecp5' of https://github...
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2019-09-30
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-09-30
whitequark
Merge pull request #1406 from whitequark/connect_rpc
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2019-09-30
Eddie Hung
Merge pull request #1397 from btut/fix/python_wrappers_...
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2019-09-30
Miodrag Milanović
Merge pull request #1416 from YosysHQ/mmicko/frontend_b...
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2019-09-30
Clifford Wolf
Merge pull request #1412 from YosysHQ/eddie/equiv_opt_a...
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2019-09-30
Eddie Hung
Add LDCE/LDPE sim library, remove from *cells_xtra...
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2019-09-30
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-09-30
Eddie Hung
Merge pull request #1414 from hzeller/improve-replace...
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2019-09-29
Eddie Hung
Merge pull request #1359 from YosysHQ/xc7dsp
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2019-09-29
Eddie Hung
FDCE_1 does not have IS_CLR_INVERTED
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2019-09-29
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-09-29
Eddie Hung
Big rework; flop info now mostly in cells_sim.v
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2019-09-27
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-09-27
Aman Goel
Merge pull request #7 from YosysHQ/master
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2019-09-25
Eddie Hung
Merge pull request #1401 from SergeyDegtyar/SergeyDegty...
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