FDCE ports to be alphabetical
[yosys.git] / techlibs / xilinx / cells_sim.v
2019-12-31 Eddie HungFDCE ports to be alphabetical
2019-12-30 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-12-28 Miodrag MilanovicMerge remote-tracking branch 'origin/master' into iopad...
2019-12-25 Marcin KościelnickiMerge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen
2019-12-23 Marcin Kościelnickixilinx: Test our DSP48A/DSP48A1 simulation models.
2019-12-20 Eddie HungMerge pull request #1588 from YosysHQ/eddie/xaiger_cleanup
2019-12-20 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-12-20 Eddie HungAdd abc9_arrival times for RAM{32,64}M
2019-12-20 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-12-20 Eddie HungMerge pull request #1585 from YosysHQ/eddie/fix_abc9_lut
2019-12-19 Eddie HungSplit into $__ABC9_ASYNC[01], do not add cell->type...
2019-12-19 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-12-19 Eddie HungMerge pull request #1581 from YosysHQ/clifford/fix1565
2019-12-19 Eddie HungMerge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
2019-12-19 Eddie HungMerge pull request #1569 from YosysHQ/eddie/fix_1531
2019-12-19 Eddie HungMerge pull request #1571 from YosysHQ/eddie/fix_1570
2019-12-19 Marcin Kościelnickixilinx: Add simulation models for remaining CLB primitives.
2019-12-18 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-12-18 David ShahMerge pull request #1563 from YosysHQ/dave/async-prld
2019-12-18 Eddie HungMerge pull request #1572 from nakengelhardt/scratchpad_pass
2019-12-18 Marcin Kościelnickixilinx: Add xilinx_dffopt pass (#1557)
2019-12-17 Eddie HungMerge pull request #1574 from YosysHQ/eddie/xilinx_lutram
2019-12-16 Eddie HungMerge pull request #1577 from gromero/for-yosys
2019-12-13 Eddie HungRAM64M8 to also have [5:0] for address
2019-12-13 Eddie HungFix RAM64M model to have 6 bit address bus
2019-12-12 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-12-12 Diego HMerge https://github.com/YosysHQ/yosys into bram_xilinx
2019-12-10 Eddie HungMerge pull request #1545 from YosysHQ/eddie/ice40_wrapc...
2019-12-07 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-12-05 Clifford WolfMerge pull request #1551 from whitequark/manual-cell...
2019-12-05 Eddie HungOh deary me
2019-12-04 Marcin Kościelnickixilinx: Add models for LUTRAM cells. (#1537)
2019-12-03 Clifford WolfMerge pull request #1524 from pepijndevos/gowindffinit
2019-11-28 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-27 Clifford WolfMerge pull request #1501 from YosysHQ/dave/mem_copy_attr
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/write_xaiger...
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-27 Eddie HungMerge branch 'master' into xaig_dff
2019-11-26 Marcin Kościelnickixilinx: Add simulation models for IOBUF and OBUFT.
2019-11-25 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-11-25 Marcin Kościelnickiclkbufmap: Add support for inverters in clock path.
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-22 Eddie HungMerge branch 'eddie/clkpart' into xaig_dff
2019-11-22 Eddie HungMerge branch 'eddie/clkpart' into xaig_dff
2019-11-22 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-11-19 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-11-19 Clifford WolfMerge pull request #1449 from pepijndevos/gowin
2019-11-19 Marcin Kościelnickixilinx: Add simulation models for MULT18X18* and DSP48A*.
2019-10-27 Clifford WolfMerge pull request #1393 from whitequark/write_verilog...
2019-10-21 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-10-18 Miodrag MilanovićMerge branch 'master' into mmicko/efinix
2019-10-18 Miodrag MilanovićMerge branch 'master' into mmicko/anlogic
2019-10-18 Miodrag MilanovićMerge branch 'master' into eddie/pr1352
2019-10-15 Benedikt TutzerMerge branch 'master' of https://github.com/YosysHQ...
2019-10-14 Clifford WolfUse "(id)" instead of "id" for types as temporary hack
2019-10-10 Miodrag MilanovićMerge pull request #1445 from YosysHQ/mwk/xilinx_ibufg
2019-10-10 Marcin Kościelnickixilinx: Add simulation model for IBUFG.
2019-10-08 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-10-08 Eddie HungMerge pull request #1432 from YosysHQ/eddie/fix1427
2019-10-08 Eddie HungMerge pull request #1433 from YosysHQ/eddie/equiv_opt_a...
2019-10-08 Eddie HungMerge pull request #1437 from YosysHQ/eddie/abc_to_abc9
2019-10-06 Eddie HungDo not require changes to cells_sim.v; try and work...
2019-10-05 Eddie HungMerge branch 'master' into eddie/abc_to_abc9
2019-10-05 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-10-04 Eddie HungMerge remote-tracking branch 'origin/eddie/abc_to_abc9...
2019-10-04 Eddie HungRename abc_* names/attributes to more precisely be...
2019-10-03 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-10-01 Eddie HungMore fixes
2019-10-01 Eddie HungEscape Verilog identifiers for legality outside of...
2019-10-01 SergeyMerge branch 'master' into SergeyDegtyar/efinix
2019-10-01 SergeyMerge branch 'master' into SergeyDegtyar/anlogic
2019-09-30 Eddie HungRemove need for $currQ port connection
2019-09-30 Eddie HungMerge branch 'SergeyDegtyar/ecp5' of https://github...
2019-09-30 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-09-30 whitequarkMerge pull request #1406 from whitequark/connect_rpc
2019-09-30 Eddie HungMerge pull request #1397 from btut/fix/python_wrappers_...
2019-09-30 Miodrag MilanovićMerge pull request #1416 from YosysHQ/mmicko/frontend_b...
2019-09-30 Clifford WolfMerge pull request #1412 from YosysHQ/eddie/equiv_opt_a...
2019-09-30 Eddie HungAdd LDCE/LDPE sim library, remove from *cells_xtra...
2019-09-30 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-09-30 Eddie HungMerge pull request #1414 from hzeller/improve-replace...
2019-09-29 Eddie HungMerge pull request #1359 from YosysHQ/xc7dsp
2019-09-29 Eddie HungFDCE_1 does not have IS_CLR_INVERTED
2019-09-29 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-09-29 Eddie HungBig rework; flop info now mostly in cells_sim.v
2019-09-27 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-09-27 Aman GoelMerge pull request #7 from YosysHQ/master
2019-09-25 Eddie HungMerge pull request #1401 from SergeyDegtyar/SergeyDegty...
next