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Merge branch 'xaig' into xc7mux
[yosys.git]
/
techlibs
/
xilinx
/
cells_xtra.sh
2019-04-16
Eddie Hung
Merge branch 'xaig' into xc7mux
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2019-04-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-04-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-04-12
Eddie Hung
Merge pull request #928 from litghost/add_xc7_sim_models
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2019-04-12
Keith Rothman
Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
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2019-04-08
Eddie Hung
Merge branch 'master' into xaig
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2019-03-22
Clifford Wolf
Merge pull request #889 from YosysHQ/clifford/fix888
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2019-03-22
Clifford Wolf
Merge pull request #890 from YosysHQ/clifford/fix887
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2019-03-22
David Shah
Merge pull request #891 from YosysHQ/xilinx_keep
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2019-03-22
David Shah
xilinx: Add keep attribute where appropriate
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2019-03-19
Eddie Hung
Merge https://github.com/YosysHQ/yosys into read_aiger
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2019-03-09
Clifford Wolf
Merge pull request #859 from smunaut/ice40_braminit
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2019-03-05
Clifford Wolf
Merge pull request #842 from litghost/merge_upstream
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2019-03-01
Keith Rothman
Changes required for VPR place and route synth_xilinx.
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2018-12-01
Clifford Wolf
Merge pull request #676 from rafaeltp/master
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2018-11-12
Clifford Wolf
Merge branch 'master' of github.com:YosysHQ/yosys
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2018-11-12
Clifford Wolf
Merge pull request #697 from eddiehung/xilinx_ps7
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2018-11-10
Eddie Hung
Add support for Xilinx PS7 block
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2018-10-17
Clifford Wolf
Merge pull request #663 from aman-goel/master
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2018-10-17
Clifford Wolf
Merge pull request #638 from udif/pr_reg_wire_error
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2018-10-16
Clifford Wolf
Merge branch 'yosys-0.8-rc'
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2018-10-13
tklam
Merge branch 'master' of https://github.com/YosysHQ...
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2018-10-05
Clifford Wolf
Merge pull request #651 from ARandomOWL/stdcells_fix
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2018-10-04
Clifford Wolf
Add inout ports to cells_xtra.v
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2016-03-19
Clifford Wolf
Added black box modules for all the 7-series design...
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