Merge branch 'xaig' into xc7mux
[yosys.git] / techlibs / xilinx / cells_xtra.sh
2019-04-16 Eddie HungMerge branch 'xaig' into xc7mux
2019-04-12 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-04-12 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-04-12 Eddie HungMerge pull request #928 from litghost/add_xc7_sim_models
2019-04-12 Keith RothmanRemove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
2019-04-08 Eddie HungMerge branch 'master' into xaig
2019-03-22 Clifford WolfMerge pull request #889 from YosysHQ/clifford/fix888
2019-03-22 Clifford WolfMerge pull request #890 from YosysHQ/clifford/fix887
2019-03-22 David ShahMerge pull request #891 from YosysHQ/xilinx_keep
2019-03-22 David Shahxilinx: Add keep attribute where appropriate
2019-03-19 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-03-09 Clifford WolfMerge pull request #859 from smunaut/ice40_braminit
2019-03-05 Clifford WolfMerge pull request #842 from litghost/merge_upstream
2019-03-01 Keith RothmanChanges required for VPR place and route synth_xilinx.
2018-12-01 Clifford WolfMerge pull request #676 from rafaeltp/master
2018-11-12 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys
2018-11-12 Clifford WolfMerge pull request #697 from eddiehung/xilinx_ps7
2018-11-10 Eddie HungAdd support for Xilinx PS7 block
2018-10-17 Clifford WolfMerge pull request #663 from aman-goel/master
2018-10-17 Clifford WolfMerge pull request #638 from udif/pr_reg_wire_error
2018-10-16 Clifford WolfMerge branch 'yosys-0.8-rc'
2018-10-13 tklamMerge branch 'master' of https://github.com/YosysHQ...
2018-10-05 Clifford WolfMerge pull request #651 from ARandomOWL/stdcells_fix
2018-10-04 Clifford WolfAdd inout ports to cells_xtra.v
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-03-19 Clifford WolfAdded black box modules for all the 7-series design...