git.libre-soc.org Git - yosys.git/history - techlibs/xilinx/drams.txt

2019-05-23	Eddie Hung	Merge remote-tracking branch 'origin/master' into xc7mux	blob \| commitdiff \| raw
2019-05-23	Eddie Hung	Merge pull request #1036 from YosysHQ/eddie/xilinx_dram	blob \| commitdiff \| raw
2019-05-23	Eddie Hung	Add "min bits" and "min wports" to xilinx dram rules	blob \| commitdiff \| raw
2016-07-08	Clifford Wolf	Merge branch 'yosys-0.5-vtr' of https://github.com...	blob \| commitdiff \| raw \| diff to current
2015-04-09	Clifford Wolf	Added memory_bram "make_outreg" feature	blob \| commitdiff \| raw \| diff to current
2015-04-09	Clifford Wolf	Xilinx DRAMS: RAM64X1D, RAM128X1D	blob \| commitdiff \| raw \| diff to current
2015-04-09	Clifford Wolf	Towards DRAM support in Xilinx flow	blob \| commitdiff \| raw \| diff to current