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Add force_downto and force_upto wire attributes.
[yosys.git]
/
techlibs
/
xilinx
/
lut4_lutrams.txt
2020-04-10
whitequark
Merge pull request #1603 from whitequark/ice40-ram_style
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2020-03-27
Claire Wolf
Merge pull request #1607 from whitequark/simplify-simpl...
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2020-03-12
Miodrag Milanović
Merge pull request #1666 from Xiretza/improve-makefile
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2020-03-03
Claire Wolf
Merge pull request #1681 from YosysHQ/eddie/fix1663
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2020-03-03
Claire Wolf
Merge pull request #1519 from YosysHQ/eddie/submod_po
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2020-02-20
Claire Wolf
Merge pull request #1642 from jjj11x/jjj11x/sv-enum
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2020-02-13
N. Engelhardt
Merge pull request #1679 from thasti/delay-parsing
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2020-02-10
Eddie Hung
Merge pull request #1670 from rodrigomelo9/master
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2020-02-10
N. Engelhardt
Merge pull request #1669 from thasti/pyosys-attrs
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2020-02-07
Marcin Kościelnicki
xilinx: Add support for LUT RAM on LUT4-based devices.
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