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Grrr
[yosys.git]
/
techlibs
/
xilinx
/
synth_xilinx.cc
2019-03-14
Eddie Hung
Revert "Add shregmap -init_msb_first and use in synth_x...
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2019-03-14
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-14
Eddie Hung
Add shregmap -init_msb_first and use in synth_xilinx
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2019-03-14
Eddie Hung
Move shregmap until after first techmap
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2019-03-09
Clifford Wolf
Merge pull request #859 from smunaut/ice40_braminit
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2019-03-05
Clifford Wolf
Merge pull request #842 from litghost/merge_upstream
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2019-03-05
Clifford Wolf
Merge pull request #850 from daveshah1/ecp5_warn_conflict
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2019-03-05
Clifford Wolf
Merge pull request #851 from kprasadvnsi/master
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2019-03-05
Clifford Wolf
Merge pull request #852 from ucb-bar/firrtlfixes
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2019-03-05
Clifford Wolf
Use "write_edif -pvector bra" for Xilinx EDIF files
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2019-03-01
Keith Rothman
Use singular for disabling of DRAM or BRAM inference.
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2019-03-01
Keith Rothman
Modify arguments to match existing style.
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2019-03-01
Keith Rothman
Changes required for VPR place and route synth_xilinx.
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2019-02-28
Eddie Hung
synth_xilinx to call shregmap with enable support
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2019-02-28
Eddie Hung
synth_xilinx to use shregmap with -params too
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2019-02-28
Eddie Hung
synth_xilinx to now have shregmap call after dff2dffe
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2019-02-11
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-01-02
Clifford Wolf
Merge pull request #770 from whitequark/opt_expr_cmp
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2019-01-02
Clifford Wolf
Merge pull request #755 from Icenowy/anlogic-dram-init
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2019-01-02
Clifford Wolf
Merge pull request #750 from Icenowy/anlogic-ff-init
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2019-01-02
Clifford Wolf
Merge pull request #773 from whitequark/opt_lut_elim_fixes
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2019-01-02
Clifford Wolf
Merge pull request #772 from whitequark/synth_lut
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2019-01-02
Clifford Wolf
Merge pull request #771 from whitequark/techmap_cmp2lut
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2019-01-02
Clifford Wolf
Merge pull request #769 from whitequark/typos
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2019-01-02
whitequark
Fix typographical and grammatical errors and inconsiste...
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2018-12-18
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2018-10-19
Clifford Wolf
Merge pull request #672 from daveshah1/fix_bram
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2018-10-18
Clifford Wolf
Merge pull request #659 from rubund/sv_interfaces
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2018-10-18
Clifford Wolf
Merge pull request #657 from mithro/xilinx-vpr
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2018-10-08
Tim 'mithro' Ansell
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.
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2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
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2018-08-18
Aman Goel
Merge pull request #3 from YosysHQ/master
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2018-08-15
Clifford Wolf
Merge pull request #573 from cr1901/msys-64
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2018-08-15
Clifford Wolf
Merge pull request #591 from hzeller/virtual-override
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2018-08-15
Clifford Wolf
Merge pull request #513 from udif/pr_reg_wire_error
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2018-07-21
Henner Zeller
Consistent use of 'override' for virtual methods in...
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2018-05-04
Clifford Wolf
Merge pull request #537 from mithro/yosys-vpr
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2018-04-18
Tim 'mithro' Ansell
Improving vpr output support.
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2018-03-07
Clifford Wolf
Add Xilinx RAM64X1D and RAM128X1D simulation models
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2016-04-23
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-04-21
Clifford Wolf
Added "yosys -D" feature
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2016-03-19
Clifford Wolf
Added black box modules for all the 7-series design...
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2016-02-13
Clifford Wolf
Run dffsr2dff in synth_xilinx
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2016-02-01
Clifford Wolf
Added "abc -luts" option, Improved Xilinx logic mapping
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2015-12-07
Clifford Wolf
Merge pull request #108 from cseed/master
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2015-10-30
Clifford Wolf
Bugfix in Xilinx LUT mapping
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2015-09-25
Clifford Wolf
Added read-enable to memory model
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2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2015-05-26
Clifford Wolf
Added output args to synth_ice40
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2015-04-09
Clifford Wolf
Towards DRAM support in Xilinx flow
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2015-04-06
Clifford Wolf
Added Xilinx bram black-box modules
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2015-04-04
Clifford Wolf
Added "dffinit", Support for initialized Xilinx DFF
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2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2015-02-15
Clifford Wolf
Added "stat" to "synth" and "synth_xilinx"
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2015-02-15
Clifford Wolf
Added final checks to "synth" and "synth_xilinx"
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2015-02-01
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2015-02-01
Clifford Wolf
no support for 6-series xilinx devices
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2015-02-01
Clifford Wolf
Added Xilinx example for Basys3 board
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2015-01-18
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2015-01-18
Clifford Wolf
Various cleanups in xilinx techlib
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2015-01-17
Clifford Wolf
Added synth_xilinx -retime -flatten
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2015-01-17
Clifford Wolf
Added MUXCY and XORCY support to synth_xilinx
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2015-01-16
Clifford Wolf
Added dff2dffe to synth_xilinx
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2015-01-15
Clifford Wolf
Added Xilinx MUXF7 and MUXF8 support
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2015-01-13
Clifford Wolf
Various cleanups in synth_xilinx command
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2015-01-06
Clifford Wolf
Various small improvements to synth_xilinx
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2015-01-05
Clifford Wolf
Towards Xilinx bram support
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2014-09-27
Clifford Wolf
namespace Yosys
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2013-11-24
Clifford Wolf
Added "techmap -share_map" option
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2013-10-27
Clifford Wolf
Added synth_xilinx command
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