Merge pull request #521 from azonenberg/for_clifford
[yosys.git] / techlibs / xilinx /
2018-03-11 Larry DoolittleSquelch trailing whitespace, including meta-whitespace
2018-03-07 Clifford WolfAdd Xilinx RAM64X1D and RAM128X1D simulation models
2017-07-10 Clifford WolfAdd techlibs/xilinx/lut2lut.v
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-21 Clifford WolfAdded "yosys -D" feature
2016-03-19 Clifford WolfAdded black box modules for all the 7-series design...
2016-02-13 Clifford WolfRun dffsr2dff in synth_xilinx
2016-02-01 Clifford WolfAdded "abc -luts" option, Improved Xilinx logic mapping
2015-12-07 Clifford WolfMerge pull request #108 from cseed/master
2015-10-30 Clifford WolfBugfix in Xilinx LUT mapping
2015-10-13 Clifford WolfAdded examples/ top-level directory
2015-09-25 Clifford WolfAdded read-enable to memory model
2015-08-22 Clifford WolfSwitched to Python 3
2015-08-16 Clifford WolfAnother bugfix for ice40 and xilinx brams_init make...
2015-08-16 Clifford WolfFixed Makefile rules for generated share files
2015-08-13 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-08-12 Clifford WolfAdjust makefiles to work with out-of-tree builds
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-05-26 Clifford WolfAdded output args to synth_ice40
2015-05-17 Clifford WolfVerific build fixes
2015-04-09 Clifford WolfImproved xilinx "bram1" test
2015-04-09 Clifford WolfAdded memory_bram "make_outreg" feature
2015-04-09 Clifford WolfXilinx DRAMS: RAM64X1D, RAM128X1D
2015-04-09 Clifford WolfTowards DRAM support in Xilinx flow
2015-04-06 Clifford WolfAdded support for initialized xilinx brams
2015-04-06 Clifford WolfAdded Xilinx test case for initialized brams
2015-04-06 Clifford WolfAdded Xilinx bram black-box modules
2015-04-04 Clifford WolfAdded "dffinit", Support for initialized Xilinx DFF
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-02-15 Clifford WolfAdded "stat" to "synth" and "synth_xilinx"
2015-02-15 Clifford WolfAdded final checks to "synth" and "synth_xilinx"
2015-02-04 Clifford WolfDisabled (unused) Xilinx tristate buffers
2015-02-01 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-02-01 Clifford Wolfno support for 6-series xilinx devices
2015-02-01 Clifford WolfRemoved old XST-based xilinx examples
2015-02-01 Clifford WolfAdded Xilinx example for Basys3 board
2015-02-01 Clifford WolfAdded missing ports and parameters to xilinx brams
2015-01-24 Clifford WolfFixed xilinx FDSE sim model
2015-01-18 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-01-18 Clifford WolfVarious cleanups in xilinx techlib
2015-01-18 Clifford WolfRefactoring of memory_bram and xilinx brams
2015-01-17 Clifford WolfAdded synth_xilinx -retime -flatten
2015-01-17 Clifford WolfAdded MUXCY and XORCY support to synth_xilinx
2015-01-16 Clifford WolfAdded dff2dffe to synth_xilinx
2015-01-16 Clifford WolfAdded more FF types to xilinx/cells.v
2015-01-16 Clifford WolfFixed xilinx bram clock inverted config
2015-01-16 Clifford WolfAdded FF cells to xilinx/cells_sim.v
2015-01-15 Clifford WolfAdded Xilinx MUXF7 and MUXF8 support
2015-01-13 Clifford WolfVarious cleanups in synth_xilinx command
2015-01-07 Clifford WolfAdded add_share_file Makefile macro
2015-01-07 Clifford Wolfadded minimalistic xilinx sim models
2015-01-07 Clifford WolfMore Xilinx bram cleanups
2015-01-07 Clifford WolfCleanups in xilinx bram descriptions
2015-01-06 Clifford WolfXilinx RAMB36/RAMB18 memory_bram support complete
2015-01-06 Clifford WolfTowards Xilinx bram support
2015-01-06 Clifford Wolfsmall fix in xilinx/brams.v
2015-01-06 Clifford WolfTowards Xilinx bram support
2015-01-06 Clifford WolfVarious small improvements to synth_xilinx
2015-01-06 Clifford WolfTowards Xilinx bram support
2015-01-06 Clifford WolfTowards Xilinx bram support
2015-01-05 Clifford WolfTowards Xilinx bram support
2015-01-04 Clifford WolfTowards Xilinx bram support
2014-12-31 Clifford WolfProgress in memory_bram
2014-12-31 Clifford WolfAdded memory_bram (not functional yet)
2014-09-27 Clifford Wolfnamespace Yosys
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-08-15 Clifford WolfRenamed $lut ports to follow A-Y naming scheme
2014-07-24 Clifford WolfAdded "make PRETTY=1"
2013-11-24 Clifford WolfAdded "techmap -share_map" option
2013-11-24 Clifford WolfFixed xilinx/example_sim_counter test bench
2013-11-23 Clifford WolfAdded more generic _TECHMAP_ wire mechanism to techmap...
2013-10-27 Clifford WolfMerge pull request #12 from jameswalmsley/master
2013-10-27 James Walmsley[EXAMPLES] Ported the mojo counter example to Zynq...
2013-10-27 Clifford WolfCleanups in xilinx examples
2013-10-27 Clifford WolfAdded synth_xilinx command
2013-10-27 Clifford WolfMoved simple xilinx counter sim example to subdir
2013-10-27 Clifford WolfXilinx mojo_counter example is now working
2013-10-26 Clifford WolfRenamed techlibs/xilinx7 to techlibs/xilinx