ice40_opt to ignore (* keep *) -ed cells
[yosys.git] / techlibs / xilinx /
2019-12-03 Clifford WolfMerge pull request #1524 from pepijndevos/gowindffinit
2019-12-02 Clifford WolfMerge pull request #1539 from YosysHQ/mwk/ilang-bounds...
2019-11-29 Miodrag MilanovićMerge pull request #1540 from YosysHQ/mwk/xilinx-bufpll
2019-11-29 Marcin Kościelnickixilinx: Add missing blackbox cell for BUFPLL.
2019-11-27 Clifford WolfMerge pull request #1501 from YosysHQ/dave/mem_copy_attr
2019-11-26 Marcin Kościelnickixilinx: Add simulation models for IOBUF and OBUFT.
2019-11-25 Marcin Kościelnickiclkbufmap: Add support for inverters in clock path.
2019-11-25 Marcin Kościelnickixilinx: Use INV instead of LUT1 when applicable
2019-11-19 Clifford WolfMerge pull request #1449 from pepijndevos/gowin
2019-11-19 Marcin Kościelnickixilinx: Add simulation models for MULT18X18* and DSP48A*.
2019-11-14 Clifford WolfMerge pull request #1444 from btut/feature/python_wrapp...
2019-11-14 Clifford WolfMerge pull request #1465 from YosysHQ/dave/ice40_timing_sim
2019-11-11 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-11-10 Clifford WolfMerge pull request #1470 from YosysHQ/clifford/subpassdoc
2019-11-06 Marcin Kościelnickisynth_xilinx: Merge blackbox primitive libraries.
2019-10-27 Clifford WolfMerge pull request #1393 from whitequark/write_verilog...
2019-10-24 David ShahMerge pull request #1455 from YosysHQ/dave/ultrascaleplus
2019-10-23 David Shahxilinx: Add URAM288 mapping for xcup
2019-10-23 David Shahxilinx: Add support for UltraScale[+] BRAM mapping
2019-10-22 Marcin Kościelnickixilinx: Support multiplier mapping for all families.
2019-10-22 Clifford WolfMerge pull request #1452 from nakengelhardt/fix_dsp_mem_reg
2019-10-21 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-10-19 Miodrag MilanovićMerge pull request #1457 from xobs/python-binary-name
2019-10-19 Sean CrossMakefile: don't assume python is called `python3`
2019-10-18 Miodrag MilanovićMerge branch 'master' into mmicko/efinix
2019-10-18 Miodrag MilanovićMerge branch 'master' into mmicko/anlogic
2019-10-18 Miodrag MilanovićMerge branch 'master' into eddie/pr1352
2019-10-17 N. EngelhardtCall memory_dff before DSP mapping to reserve registers...
2019-10-15 Benedikt TutzerMerge branch 'master' of https://github.com/YosysHQ...
2019-10-14 Clifford WolfUse "(id)" instead of "id" for types as temporary hack
2019-10-10 Miodrag MilanovićMerge pull request #1445 from YosysHQ/mwk/xilinx_ibufg
2019-10-10 Marcin Kościelnickixilinx: Add simulation model for IBUFG.
2019-10-08 Eddie HungMerge pull request #1432 from YosysHQ/eddie/fix1427
2019-10-08 Eddie HungMerge pull request #1433 from YosysHQ/eddie/equiv_opt_a...
2019-10-08 Eddie HungMerge pull request #1437 from YosysHQ/eddie/abc_to_abc9
2019-10-08 Eddie HungMerge pull request #1438 from YosysHQ/eddie/xilinx_dsp_...
2019-10-05 Miodrag MilanovićMerge pull request #1436 from YosysHQ/mmicko/msvc_fix
2019-10-05 Eddie HungAdd comment on why partial multipliers are 18x18
2019-10-05 Eddie HungFix typo in check_label()
2019-10-05 Eddie HungMerge branch 'master' into eddie/abc_to_abc9
2019-10-05 Eddie HungAdd temporary `abc9 -nomfs` and use for `synth_xilinx...
2019-10-05 Eddie HungRemove DSP48E1 from *_cells_xtra.v
2019-10-04 Eddie HungRename abc_* names/attributes to more precisely be...
2019-10-01 SergeyMerge branch 'master' into SergeyDegtyar/efinix
2019-10-01 SergeyMerge branch 'master' into SergeyDegtyar/anlogic
2019-09-30 Eddie HungMerge branch 'SergeyDegtyar/ecp5' of https://github...
2019-09-30 whitequarkMerge pull request #1406 from whitequark/connect_rpc
2019-09-30 Eddie HungMerge pull request #1397 from btut/fix/python_wrappers_...
2019-09-30 Miodrag MilanovićMerge pull request #1416 from YosysHQ/mmicko/frontend_b...
2019-09-30 Clifford WolfMerge pull request #1412 from YosysHQ/eddie/equiv_opt_a...
2019-09-30 Eddie HungAdd LDCE/LDPE sim library, remove from *cells_xtra...
2019-09-30 Marcin Kościelnickisynth_xilinx: Support latches, remove used-up FF init...
2019-09-30 Eddie HungMerge pull request #1414 from hzeller/improve-replace...
2019-09-29 Eddie HungMerge pull request #1359 from YosysHQ/xc7dsp
2019-09-29 Clifford WolfMerge pull request #1411 from aman-goel/YosysHQ-master
2019-09-28 Eddie HungFix box name
2019-09-27 Eddie HungRe-order
2019-09-27 Aman GoelMerge pull request #7 from YosysHQ/master
2019-09-27 Clifford WolfMerge pull request #1404 from YosysHQ/fix_gzip_macos
2019-09-26 Eddie HungMissing an '&'
2019-09-26 Eddie HungTypo
2019-09-26 Eddie Hungselect once
2019-09-26 Eddie HungStop trying to be too smart by prematurely optimising
2019-09-25 Eddie HungMerge pull request #1401 from SergeyDegtyar/SergeyDegty...
2019-09-25 Eddie HungCall 'wreduce' after mul2dsp to avoid unextend()
2019-09-25 Eddie HungOops. Actually use __NAME__ in ABC_DSP48E1 macro
2019-09-24 Eddie HungAdd (* techmap_autopurge *) to abc_unmap.v too
2019-09-24 Eddie HungAdd techmap_autopurge to outputs in abc_map.v too
2019-09-24 Eddie HungRevert "Add a xilinx_finalise pass"
2019-09-24 Eddie HungRevert "Remove (* techmap_autopurge *) from abc_unmap...
2019-09-24 Eddie HungRevert "Vivado does not like zero width port connections"
2019-09-24 Eddie HungVivado does not like zero width port connections
2019-09-24 Eddie HungRemove (* techmap_autopurge *) from abc_unmap.v since...
2019-09-24 Eddie HungAdd a xilinx_finalise pass
2019-09-23 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-09-20 Eddie HungGrammar
2019-09-20 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-09-20 Eddie HungRe-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine...
2019-09-20 Eddie HungTidy up, fix undriven
2019-09-20 Eddie Hung$__ABC_REG to have WIDTH parameter
2019-09-20 Eddie HungFix DSP48E1 timing by breaking P path if MREG or PREG
2019-09-20 Eddie HungRevert "Different approach to timing"
2019-09-20 Eddie HungDifferent approach to timing
2019-09-19 Eddie HungSuppress $anyseq warnings
2019-09-19 Eddie HungUse (* techmap_autopurge *) to suppress techmap warnings
2019-09-19 Eddie HungD is 25 bits not 24 bits wide
2019-09-19 Eddie HungMerge remote-tracking branch 'origin/clifford/fix1381...
2019-09-19 Eddie Hungsynth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB...
2019-09-19 Marcin KościelnickiUse extractinv for synth_xilinx -ise
2019-09-18 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-09-18 Eddie HungMerge pull request #1355 from YosysHQ/eddie/peepopt_dff...
2019-09-18 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-09-18 Eddie HungFix copy-paste
2019-09-18 Eddie HungMis-spell
2019-09-18 Eddie HungAdd pattern detection support for DSP48E1 model, check...
2019-09-18 Eddie HungMerge pull request #1379 from mmicko/sim_models
2019-09-15 Eddie HungMerge pull request #1374 from YosysHQ/eddie/fix1371
2019-09-15 Marcin Kościelnickixilinx: Make blackbox library family-dependent.
2019-09-14 Eddie HungAdd `undef DSP48E1_INST
2019-09-13 Eddie HungFix D -> P{,COUT} delay
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