Different approach to timing
[yosys.git] / techlibs / xilinx /
2019-08-21 Eddie Hungabc9 to perform new 'map_ffs' before 'map_luts'
2019-08-21 Eddie HungMerge branch 'eddie/fix_mem2reg' into eddie/xilinx_srl
2019-08-21 Eddie HungAdd init support
2019-08-21 Eddie HungUse semicolon
2019-08-21 Eddie Hungtechmap before read
2019-08-21 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_...
2019-08-21 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_...
2019-08-21 Eddie HungAdd abc_arrival to SRL*
2019-08-21 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-08-21 Eddie HungOops
2019-08-21 Eddie HungMerge branch 'eddie/fix_techmap' into xaig_arrival
2019-08-21 Eddie Hungxilinx to use abc_map.v with -max_iter 1
2019-08-21 Eddie HungAdd reference to FD* timing
2019-08-21 Eddie HungRemove sequential extension
2019-08-21 Eddie HungRemove SRL* delays from cells_sim.v
2019-08-21 Eddie HungLUTMUX -> LUTMUX6
2019-08-21 Eddie HungCleanup techmap in map_luts
2019-08-21 Eddie HungMove `techmap abc_map.v` into map_luts
2019-08-21 Eddie HungRemove delays from abc_map.v
2019-08-21 Eddie HungTypo
2019-08-21 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-08-20 Eddie HungWrap SRL{16,32} too
2019-08-20 Eddie HungWrap LUTRAMs in order to capture comb/seq behaviour
2019-08-20 Eddie HungAdd LUTRAM delays
2019-08-20 Eddie HungRemove mapping rules
2019-08-20 Eddie HungMerge pull request #1209 from YosysHQ/eddie/synth_xilinx
2019-08-20 Eddie HungRemove -icells
2019-08-20 Eddie HungUse abc_{map,unmap,model}.v
2019-08-20 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-08-20 Eddie HungMerge pull request #1304 from YosysHQ/eddie/abc9_refactor
2019-08-20 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-19 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-08-19 Eddie HungAdd arrival times for SRL outputs
2019-08-19 Eddie HungAdd BRAM arrival times
2019-08-19 Eddie HungAdd reference to source of Tclktoq timing
2019-08-19 Eddie Hung Add 'abc_arrival' attribute for flop outputs
2019-08-19 Eddie HungUpdate box timings
2019-08-19 Eddie HungMove from cell attr to module attr
2019-08-19 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-08-19 Eddie HungUnify abc_carry_{in,out} into abc_carry and use port...
2019-08-19 Eddie HungUse attributes instead of params
2019-08-16 Eddie HungMerge branch 'eddie/abc9_refactor' into xaig_dff
2019-08-16 Eddie HungAttach abc_scc_break, abc_carry_{in,out} attr to ports...
2019-08-16 Eddie HungMerge pull request #1250 from bwidawsk/master
2019-08-16 Eddie HungMerge https://github.com/bogdanvuk/yosys into bogdanvuk...
2019-08-16 Eddie HungMerge remote-tracking branch 'origin/master' into mwk...
2019-08-15 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-08-15 Eddie HungMerge branch 'xc7dsp' of github.com:YosysHQ/yosys into...
2019-08-13 Marcin Kościelnickimove attributes to wires
2019-08-13 Eddie HungAdd assign PCOUT = P to DSP48E1
2019-08-13 Marcin Kościelnickiminor review fixes
2019-08-13 Eddie HungAdd DSP_A_MAXWIDTH_PARTIAL, refactor
2019-08-13 David Shahxilinx: Rework labels for faster Verilator testing
2019-08-13 Marcin Kościelnickireview fixes
2019-08-12 Marcin KościelnickiAdd clock buffer insertion pass, improve iopadmap.
2019-08-12 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-08-12 Serge BazanskiMerge pull request #1152 from 1138-4EB/feat-docker
2019-08-12 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-10 Clifford WolfMerge pull request #1258 from YosysHQ/eddie/cleanup
2019-08-09 Eddie HungPack partial-product adder DSP48E1 packing
2019-08-08 Eddie HungRemove signed from ports in +/xilinx/dsp_map.v
2019-08-08 Eddie HungCombine techmap calls
2019-08-08 Eddie HungMove xilinx_dsp to before alumacc
2019-08-08 Eddie HungINMODE is 5 bits
2019-08-08 Eddie HungFix copy-pasta typo
2019-08-08 David ShahMerge branch 'xc7dsp' of github.com:YosysHQ/yosys into...
2019-08-08 David ShahDSP48E1 sim model: add SIMD tests
2019-08-08 David ShahDSP48E1 model: test CE inputs
2019-08-08 David ShahDSP48E1 sim model: fix seq tests and add preadder tests
2019-08-08 David ShahDSP48E1 sim model: seq test working
2019-08-08 David ShahDSP48E1 sim model: Comb, no pre-adder, mode working
2019-08-08 David Shah[wip] sim model testing
2019-08-08 David Shah[wip] sim model testing
2019-08-07 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-08-07 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-07 Eddie Hungstoi -> atoi
2019-08-07 Jim LawsonMerge branch 'master' into firrtl_err_on_unsupported_cell
2019-08-07 David Shah[wip] DSP48E1 sim model improvements
2019-08-07 Clifford WolfMerge pull request #1240 from ucb-bar/firrtl-properties...
2019-08-07 David ShahMerge pull request #1241 from YosysHQ/clifford/jsonfix
2019-08-06 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-06 David Shah[wip] DSP48E1 sim model improvements
2019-08-06 David Shah[wip] DSP48E1 sim model improvements
2019-08-03 whitequarkMerge pull request #1242 from jfng/fix-proc_prune-partial
2019-08-02 Clifford WolfMerge pull request #1238 from mmicko/vsbuild_fix
2019-08-02 Clifford WolfMerge pull request #1239 from mmicko/mingw_fix
2019-08-01 Eddie HungChange $__softmul back to $mul
2019-08-01 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-08-01 Eddie HungMerge pull request #1236 from YosysHQ/eddie/xc6s_brams_map
2019-07-30 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-07-29 Eddie HungRST -> RSTBRST for RAMB8BWER
2019-07-27 David ShahMerge pull request #1226 from YosysHQ/dave/gzip
2019-07-25 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-07-25 Clifford WolfMerge branch 'ZirconiumX-synth_intel_m9k'
2019-07-25 Clifford WolfMerge pull request #1218 from ZirconiumX/synth_intel_iopads
2019-07-25 Clifford WolfMerge pull request #1219 from jakobwenzel/objIterator
2019-07-25 Eddie HungMerge pull request #1224 from YosysHQ/xilinx_fix_ff
2019-07-25 David Shahxilinx: Fix missing cell name underscore in cells_map.v
2019-07-24 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-07-19 Eddie HungMerge remote-tracking branch 'origin/eddie/wreduce_add...
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