ice40_opt to ignore (* keep *) -ed cells
[yosys.git] / techlibs /
2019-12-03 Eddie Hungice40_opt to ignore (* keep *) -ed cells
2019-12-03 Clifford WolfMerge pull request #1524 from pepijndevos/gowindffinit
2019-12-03 Pepijn de VosUse -match-init to not synth contradicting init values
2019-12-02 Clifford WolfMerge pull request #1539 from YosysHQ/mwk/ilang-bounds...
2019-11-29 Miodrag MilanovićMerge pull request #1540 from YosysHQ/mwk/xilinx-bufpll
2019-11-29 Marcin Kościelnickixilinx: Add missing blackbox cell for BUFPLL.
2019-11-27 Clifford WolfMerge pull request #1501 from YosysHQ/dave/mem_copy_attr
2019-11-26 Marcin Kościelnickixilinx: Add simulation models for IOBUF and OBUFT.
2019-11-25 Marcin Kościelnickiclkbufmap: Add support for inverters in clock path.
2019-11-25 Marcin Kościelnickixilinx: Use INV instead of LUT1 when applicable
2019-11-25 Pepijn de Vosattempt to fix formatting
2019-11-25 Pepijn de Vosgowin: add and test dff init values
2019-11-23 Eddie HungMerge pull request #1520 from pietrmar/fix-1463
2019-11-23 Martin Pietrykacoolrunner2: remove spurious log_pop() call, fixes...
2019-11-22 Clifford WolfMerge pull request #1511 from YosysHQ/dave/always
2019-11-22 Marcin Kościelnickigowin: Add missing .gitignore entries
2019-11-19 Clifford WolfMerge pull request #1449 from pepijndevos/gowin
2019-11-19 Pepijn de VosRemove dff init altogether
2019-11-19 Marcin Kościelnickixilinx: Add simulation models for MULT18X18* and DSP48A*.
2019-11-18 Pepijn de Vosadd help for nowidelut and abc9 options
2019-11-18 whitequarkMerge pull request #1494 from whitequark/write_verilog...
2019-11-17 Clifford WolfMerge pull request #1492 from YosysHQ/dave/wreduce...
2019-11-16 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-11-15 David Shahecp5: Use new autoname pass for better cell/net names
2019-11-14 Clifford WolfMerge pull request #1490 from YosysHQ/clifford/autoname
2019-11-14 Clifford WolfMerge pull request #1444 from btut/feature/python_wrapp...
2019-11-14 Clifford WolfMerge pull request #1465 from YosysHQ/dave/ice40_timing_sim
2019-11-14 Clifford WolfMerge branch 'label-bads-btor' of https://github.com...
2019-11-13 Clifford WolfAdd "autoname" pass and use it in "synth_ice40"
2019-11-13 whitequarkMerge pull request #1488 from whitequark/flowmap-fixes
2019-11-12 Clifford WolfMerge pull request #1484 from YosysHQ/clifford/cmp2luteqne
2019-11-11 Pepijn de Vosfix fsm test with proper clock enable polarity
2019-11-11 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-11-11 Clifford WolfDo not map $eq and $ne in cmp2lut, only proper arithmet...
2019-11-10 Clifford WolfMerge pull request #1470 from YosysHQ/clifford/subpassdoc
2019-11-06 Pepijn de Vosfix wide luts
2019-11-06 Marcin Kościelnickisynth_xilinx: Merge blackbox primitive libraries.
2019-10-28 Pepijn de Vosadd IOBUF
2019-10-28 Pepijn de Vosadd tristate buffer and test
2019-10-28 Pepijn de VosMore formatting
2019-10-28 Pepijn de Vosreally really fix formatting maybe
2019-10-28 Pepijn de Vosundo formatting fuckup
2019-10-28 Pepijn de Vosadd wide luts
2019-10-28 Pepijn de Vosadd 32-bit BRAM and byte-enables
2019-10-27 Clifford WolfMerge pull request #1393 from whitequark/write_verilog...
2019-10-24 Pepijn de VosALU sim tweaks
2019-10-24 David ShahMerge pull request #1455 from YosysHQ/dave/ultrascaleplus
2019-10-23 David Shahice40: Add post-pnr ICESTORM_RAM model and fix FFs
2019-10-23 David Shahice40: Support for post-pnr timing simulation
2019-10-23 David Shahxilinx: Add URAM288 mapping for xcup
2019-10-23 David Shahxilinx: Add support for UltraScale[+] BRAM mapping
2019-10-22 Marcin Kościelnickixilinx: Support multiplier mapping for all families.
2019-10-22 Clifford WolfMerge pull request #1452 from nakengelhardt/fix_dsp_mem_reg
2019-10-21 Pepijn de Vosadd a few more missing dff
2019-10-21 Pepijn de Vosadd negedge DFF
2019-10-21 Pepijn de Vosuse ADDSUB ALU mode to remove inverters
2019-10-21 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-10-20 David Shahecp5: Pass -nomfs to abc9
2019-10-19 Miodrag MilanovićMerge pull request #1457 from xobs/python-binary-name
2019-10-19 Sean CrossMakefile: don't assume python is called `python3`
2019-10-18 Miodrag MilanovićMerge pull request #1435 from YosysHQ/mmicko/efinix
2019-10-18 Miodrag MilanovićMerge branch 'master' into mmicko/efinix
2019-10-18 Miodrag MilanovićMerge branch 'master' into mmicko/anlogic
2019-10-18 Miodrag MilanovićMerge branch 'master' into eddie/pr1352
2019-10-17 N. EngelhardtCall memory_dff before DSP mapping to reserve registers...
2019-10-16 Pepijn de Vosremove duplicate DFFR
2019-10-15 Benedikt TutzerMerge branch 'master' of https://github.com/YosysHQ...
2019-10-14 Clifford WolfMerge pull request #1448 from YosysHQ/daveshah1-sv...
2019-10-14 David ShahMerge pull request #1446 from YosysHQ/dave/ecp5-ioff
2019-10-14 Clifford WolfUse "(id)" instead of "id" for types as temporary hack
2019-10-11 David Shahecp5: Add ECLKBRIDGECS blackbox
2019-10-10 David Shahecp5: Add attrmvcp to copy syn_useioff to driving FF
2019-10-10 David Shahecp5: Set syn_useioff on IO FFs to enable packing
2019-10-10 Miodrag MilanovićMerge pull request #1445 from YosysHQ/mwk/xilinx_ibufg
2019-10-10 Marcin Kościelnickixilinx: Add simulation model for IBUFG.
2019-10-08 Eddie HungMerge pull request #1432 from YosysHQ/eddie/fix1427
2019-10-08 Eddie HungMerge pull request #1433 from YosysHQ/eddie/equiv_opt_a...
2019-10-08 Eddie HungMerge pull request #1437 from YosysHQ/eddie/abc_to_abc9
2019-10-08 Eddie HungMerge pull request #1438 from YosysHQ/eddie/xilinx_dsp_...
2019-10-05 Miodrag MilanovićMerge pull request #1436 from YosysHQ/mmicko/msvc_fix
2019-10-05 Eddie HungAdd comment on why partial multipliers are 18x18
2019-10-05 Eddie HungFix typo in check_label()
2019-10-05 Eddie HungMerge branch 'master' into eddie/abc_to_abc9
2019-10-05 Eddie HungAdd temporary `abc9 -nomfs` and use for `synth_xilinx...
2019-10-05 Eddie HungRemove DSP48E1 from *_cells_xtra.v
2019-10-04 Eddie HungRename abc_* names/attributes to more precisely be...
2019-10-04 Eddie HungPanic over. Model was elsewhere. Re-arrange for consistency
2019-10-04 Eddie HungOops
2019-10-04 Eddie HungOhmilord this wasn't added all this time!?!
2019-10-04 Miodrag MilanovicFF should be initialized to 0
2019-10-04 Miodrag MilanovicAdd missing latch mapping
2019-10-04 Miodrag MilanovicMerge branch 'SergeyDegtyar/efinix' of https://github...
2019-10-04 Miodrag MilanovicMerge branch 'SergeyDegtyar/anlogic' of https://github...
2019-10-03 Clifford WolfMerge pull request #1419 from YosysHQ/eddie/lazy_derive
2019-10-03 Clifford WolfMerge pull request #1422 from YosysHQ/eddie/aigmap_select
2019-10-03 Clifford WolfMerge pull request #1429 from YosysHQ/clifford/checkmapped
2019-10-03 David ShahMerge pull request #1425 from YosysHQ/dave/ecp5_pdp16
2019-10-01 David Shahecp5: Fix shuffle_enable port
2019-10-01 David Shahecp5: Add support for mapping 36-bit wide PDP BRAMs
2019-10-01 SergeyMerge branch 'master' into SergeyDegtyar/efinix
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