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Revert "Add test that is expecting to fail"
[yosys.git]
/
techlibs
/
2019-10-08
Eddie Hung
Merge pull request #1432 from YosysHQ/eddie/fix1427
tree
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commitdiff
2019-10-08
Eddie Hung
Merge pull request #1433 from YosysHQ/eddie/equiv_opt_a...
tree
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commitdiff
2019-10-08
Eddie Hung
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
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commitdiff
2019-10-08
Eddie Hung
Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_...
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commitdiff
2019-10-05
Miodrag Milanović
Merge pull request #1436 from YosysHQ/mmicko/msvc_fix
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commitdiff
2019-10-05
Eddie Hung
Add comment on why partial multipliers are 18x18
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commitdiff
2019-10-05
Eddie Hung
Fix typo in check_label()
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commitdiff
2019-10-05
Eddie Hung
Merge branch 'master' into eddie/abc_to_abc9
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commitdiff
2019-10-05
Eddie Hung
Add temporary `abc9 -nomfs` and use for `synth_xilinx...
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commitdiff
2019-10-05
Eddie Hung
Remove DSP48E1 from *_cells_xtra.v
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commitdiff
2019-10-04
Eddie Hung
Rename abc_* names/attributes to more precisely be...
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commitdiff
2019-10-04
Eddie Hung
Panic over. Model was elsewhere. Re-arrange for consistency
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commitdiff
2019-10-04
Eddie Hung
Oops
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commitdiff
2019-10-04
Eddie Hung
Ohmilord this wasn't added all this time!?!
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commitdiff
2019-10-03
Clifford Wolf
Merge pull request #1419 from YosysHQ/eddie/lazy_derive
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commitdiff
2019-10-03
Clifford Wolf
Merge pull request #1422 from YosysHQ/eddie/aigmap_select
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commitdiff
2019-10-03
Clifford Wolf
Merge pull request #1429 from YosysHQ/clifford/checkmapped
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commitdiff
2019-10-03
David Shah
Merge pull request #1425 from YosysHQ/dave/ecp5_pdp16
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commitdiff
2019-10-01
David Shah
ecp5: Fix shuffle_enable port
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commitdiff
2019-10-01
David Shah
ecp5: Add support for mapping 36-bit wide PDP BRAMs
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commitdiff
2019-09-30
whitequark
Merge pull request #1406 from whitequark/connect_rpc
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commitdiff
2019-09-30
Eddie Hung
Merge pull request #1397 from btut/fix/python_wrappers_...
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commitdiff
2019-09-30
Miodrag Milanović
Merge pull request #1416 from YosysHQ/mmicko/frontend_b...
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commitdiff
2019-09-30
Clifford Wolf
Merge pull request #1412 from YosysHQ/eddie/equiv_opt_a...
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commitdiff
2019-09-30
Eddie Hung
Add LDCE/LDPE sim library, remove from *cells_xtra...
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commitdiff
2019-09-30
Marcin Kościelnicki
synth_xilinx: Support latches, remove used-up FF init...
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commitdiff
2019-09-30
Eddie Hung
Merge pull request #1414 from hzeller/improve-replace...
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commitdiff
2019-09-29
Eddie Hung
Merge pull request #1359 from YosysHQ/xc7dsp
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commitdiff
2019-09-29
Clifford Wolf
Merge pull request #1411 from aman-goel/YosysHQ-master
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commitdiff
2019-09-28
Eddie Hung
Fix box name
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commitdiff
2019-09-27
Eddie Hung
Re-order
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commitdiff
2019-09-27
Eddie Hung
Missing (* mul2dsp *) for sliceB
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commitdiff
2019-09-27
Aman Goel
Merge pull request #7 from YosysHQ/master
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commitdiff
2019-09-27
Clifford Wolf
Merge pull request #1404 from YosysHQ/fix_gzip_macos
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commitdiff
2019-09-26
Eddie Hung
Missing an '&'
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commitdiff
2019-09-26
Eddie Hung
Combine 'flatten' & 'coarse' labels in synth_ecp5 so...
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commitdiff
2019-09-26
Eddie Hung
Typo
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commitdiff
2019-09-26
Eddie Hung
select once
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commitdiff
2019-09-26
Eddie Hung
Stop trying to be too smart by prematurely optimising
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commitdiff
2019-09-26
Eddie Hung
mul2dsp.v slice names
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commitdiff
2019-09-26
Eddie Hung
Remove unnecessary check for A_SIGNED != B_SIGNED;...
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commitdiff
2019-09-26
Eddie Hung
Revert "Remove _TECHMAP_CELLTYPE_ check since all ...
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commitdiff
2019-09-26
Eddie Hung
Revert "No need for $__mul anymore?"
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commitdiff
2019-09-26
Eddie Hung
Only wreduce on t:$add
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commitdiff
2019-09-25
Eddie Hung
Remove _TECHMAP_CELLTYPE_ check since all $mul
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commitdiff
2019-09-25
Eddie Hung
Merge pull request #1401 from SergeyDegtyar/SergeyDegty...
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commitdiff
2019-09-25
Eddie Hung
No need for $__mul anymore?
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commitdiff
2019-09-25
Eddie Hung
Call 'wreduce' after mul2dsp to avoid unextend()
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commitdiff
2019-09-25
Eddie Hung
Oops. Actually use __NAME__ in ABC_DSP48E1 macro
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commitdiff
2019-09-24
Eddie Hung
Add (* techmap_autopurge *) to abc_unmap.v too
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commitdiff
2019-09-24
Eddie Hung
Add techmap_autopurge to outputs in abc_map.v too
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commitdiff
2019-09-24
Eddie Hung
Revert "Add a xilinx_finalise pass"
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commitdiff
2019-09-24
Eddie Hung
Revert "Remove (* techmap_autopurge *) from abc_unmap...
tree
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commitdiff
2019-09-24
Eddie Hung
Revert "Vivado does not like zero width port connections"
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commitdiff
2019-09-24
Eddie Hung
Vivado does not like zero width port connections
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commitdiff
2019-09-24
Eddie Hung
Remove (* techmap_autopurge *) from abc_unmap.v since...
tree
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commitdiff
2019-09-24
Eddie Hung
Add a xilinx_finalise pass
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commitdiff
2019-09-23
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
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commitdiff
2019-09-20
Eddie Hung
Grammar
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commitdiff
2019-09-20
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
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commitdiff
2019-09-20
Eddie Hung
Fix signedness bug
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commitdiff
2019-09-20
Eddie Hung
Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine...
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commitdiff
2019-09-20
Eddie Hung
Revert "Move mul2dsp before wreduce"
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commitdiff
2019-09-20
Eddie Hung
Move mul2dsp before wreduce
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commitdiff
2019-09-20
Eddie Hung
Tidy up, fix undriven
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commitdiff
2019-09-20
Eddie Hung
$__ABC_REG to have WIDTH parameter
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commitdiff
2019-09-20
Eddie Hung
Fix DSP48E1 timing by breaking P path if MREG or PREG
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commitdiff
2019-09-20
Eddie Hung
Revert "Different approach to timing"
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commitdiff
2019-09-20
Eddie Hung
Different approach to timing
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commitdiff
2019-09-19
Eddie Hung
Suppress $anyseq warnings
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commitdiff
2019-09-19
Eddie Hung
Use (* techmap_autopurge *) to suppress techmap warnings
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commitdiff
2019-09-19
Eddie Hung
D is 25 bits not 24 bits wide
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commitdiff
2019-09-19
Eddie Hung
Merge remote-tracking branch 'origin/clifford/fix1381...
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commitdiff
2019-09-19
Eddie Hung
synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB...
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commitdiff
2019-09-19
Eddie Hung
Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2
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commitdiff
2019-09-19
Marcin Kościelnicki
Use extractinv for synth_xilinx -ise
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commitdiff
2019-09-18
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
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commitdiff
2019-09-18
Eddie Hung
Merge pull request #1355 from YosysHQ/eddie/peepopt_dff...
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commitdiff
2019-09-18
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
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commitdiff
2019-09-18
Eddie Hung
Fix copy-paste
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commitdiff
2019-09-18
Eddie Hung
Mis-spell
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commitdiff
2019-09-18
Eddie Hung
Add pattern detection support for DSP48E1 model, check...
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commitdiff
2019-09-18
Eddie Hung
Merge pull request #1379 from mmicko/sim_models
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commitdiff
2019-09-18
Miodrag Milanovic
make note that it is for latch mode
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commitdiff
2019-09-18
Miodrag Milanovic
better lut handling
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commitdiff
2019-09-18
Miodrag Milanovic
better handling of lut and begin/end add
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commitdiff
2019-09-15
Eddie Hung
Merge pull request #1374 from YosysHQ/eddie/fix1371
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commitdiff
2019-09-15
Marcin Kościelnicki
xilinx: Make blackbox library family-dependent.
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commitdiff
2019-09-15
Miodrag Milanovic
Added simulation models for Efinix and Anlogic
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commitdiff
2019-09-14
Eddie Hung
Add `undef DSP48E1_INST
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commitdiff
2019-09-13
Eddie Hung
Fix D -> P{,COUT} delay
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commitdiff
2019-09-13
Eddie Hung
Add no MULT no DPORT config
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commitdiff
2019-09-13
Eddie Hung
Add support for MULT and DPORT
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commitdiff
2019-09-13
Eddie Hung
Refine diagram
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commitdiff
2019-09-13
Eddie Hung
Add an ASCII drawing
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commitdiff
2019-09-13
Eddie Hung
Finish explanation
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commitdiff
2019-09-13
Eddie Hung
Rename to techmap_guard
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commitdiff
2019-09-13
Eddie Hung
Initial DSP48E1 box support
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commitdiff
2019-09-13
Eddie Hung
Set more ports explicitly
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commitdiff
2019-09-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
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commitdiff
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