Revert "Add test that is expecting to fail"
[yosys.git] / techlibs /
2019-10-08 Eddie HungMerge pull request #1432 from YosysHQ/eddie/fix1427
2019-10-08 Eddie HungMerge pull request #1433 from YosysHQ/eddie/equiv_opt_a...
2019-10-08 Eddie HungMerge pull request #1437 from YosysHQ/eddie/abc_to_abc9
2019-10-08 Eddie HungMerge pull request #1438 from YosysHQ/eddie/xilinx_dsp_...
2019-10-05 Miodrag MilanovićMerge pull request #1436 from YosysHQ/mmicko/msvc_fix
2019-10-05 Eddie HungAdd comment on why partial multipliers are 18x18
2019-10-05 Eddie HungFix typo in check_label()
2019-10-05 Eddie HungMerge branch 'master' into eddie/abc_to_abc9
2019-10-05 Eddie HungAdd temporary `abc9 -nomfs` and use for `synth_xilinx...
2019-10-05 Eddie HungRemove DSP48E1 from *_cells_xtra.v
2019-10-04 Eddie HungRename abc_* names/attributes to more precisely be...
2019-10-04 Eddie HungPanic over. Model was elsewhere. Re-arrange for consistency
2019-10-04 Eddie HungOops
2019-10-04 Eddie HungOhmilord this wasn't added all this time!?!
2019-10-03 Clifford WolfMerge pull request #1419 from YosysHQ/eddie/lazy_derive
2019-10-03 Clifford WolfMerge pull request #1422 from YosysHQ/eddie/aigmap_select
2019-10-03 Clifford WolfMerge pull request #1429 from YosysHQ/clifford/checkmapped
2019-10-03 David ShahMerge pull request #1425 from YosysHQ/dave/ecp5_pdp16
2019-10-01 David Shahecp5: Fix shuffle_enable port
2019-10-01 David Shahecp5: Add support for mapping 36-bit wide PDP BRAMs
2019-09-30 whitequarkMerge pull request #1406 from whitequark/connect_rpc
2019-09-30 Eddie HungMerge pull request #1397 from btut/fix/python_wrappers_...
2019-09-30 Miodrag MilanovićMerge pull request #1416 from YosysHQ/mmicko/frontend_b...
2019-09-30 Clifford WolfMerge pull request #1412 from YosysHQ/eddie/equiv_opt_a...
2019-09-30 Eddie HungAdd LDCE/LDPE sim library, remove from *cells_xtra...
2019-09-30 Marcin Kościelnickisynth_xilinx: Support latches, remove used-up FF init...
2019-09-30 Eddie HungMerge pull request #1414 from hzeller/improve-replace...
2019-09-29 Eddie HungMerge pull request #1359 from YosysHQ/xc7dsp
2019-09-29 Clifford WolfMerge pull request #1411 from aman-goel/YosysHQ-master
2019-09-28 Eddie HungFix box name
2019-09-27 Eddie HungRe-order
2019-09-27 Eddie HungMissing (* mul2dsp *) for sliceB
2019-09-27 Aman GoelMerge pull request #7 from YosysHQ/master
2019-09-27 Clifford WolfMerge pull request #1404 from YosysHQ/fix_gzip_macos
2019-09-26 Eddie HungMissing an '&'
2019-09-26 Eddie HungCombine 'flatten' & 'coarse' labels in synth_ecp5 so...
2019-09-26 Eddie HungTypo
2019-09-26 Eddie Hungselect once
2019-09-26 Eddie HungStop trying to be too smart by prematurely optimising
2019-09-26 Eddie Hungmul2dsp.v slice names
2019-09-26 Eddie HungRemove unnecessary check for A_SIGNED != B_SIGNED;...
2019-09-26 Eddie HungRevert "Remove _TECHMAP_CELLTYPE_ check since all ...
2019-09-26 Eddie HungRevert "No need for $__mul anymore?"
2019-09-26 Eddie HungOnly wreduce on t:$add
2019-09-25 Eddie HungRemove _TECHMAP_CELLTYPE_ check since all $mul
2019-09-25 Eddie HungMerge pull request #1401 from SergeyDegtyar/SergeyDegty...
2019-09-25 Eddie HungNo need for $__mul anymore?
2019-09-25 Eddie HungCall 'wreduce' after mul2dsp to avoid unextend()
2019-09-25 Eddie HungOops. Actually use __NAME__ in ABC_DSP48E1 macro
2019-09-24 Eddie HungAdd (* techmap_autopurge *) to abc_unmap.v too
2019-09-24 Eddie HungAdd techmap_autopurge to outputs in abc_map.v too
2019-09-24 Eddie HungRevert "Add a xilinx_finalise pass"
2019-09-24 Eddie HungRevert "Remove (* techmap_autopurge *) from abc_unmap...
2019-09-24 Eddie HungRevert "Vivado does not like zero width port connections"
2019-09-24 Eddie HungVivado does not like zero width port connections
2019-09-24 Eddie HungRemove (* techmap_autopurge *) from abc_unmap.v since...
2019-09-24 Eddie HungAdd a xilinx_finalise pass
2019-09-23 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-09-20 Eddie HungGrammar
2019-09-20 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-09-20 Eddie HungFix signedness bug
2019-09-20 Eddie HungRe-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine...
2019-09-20 Eddie HungRevert "Move mul2dsp before wreduce"
2019-09-20 Eddie HungMove mul2dsp before wreduce
2019-09-20 Eddie HungTidy up, fix undriven
2019-09-20 Eddie Hung$__ABC_REG to have WIDTH parameter
2019-09-20 Eddie HungFix DSP48E1 timing by breaking P path if MREG or PREG
2019-09-20 Eddie HungRevert "Different approach to timing"
2019-09-20 Eddie HungDifferent approach to timing
2019-09-19 Eddie HungSuppress $anyseq warnings
2019-09-19 Eddie HungUse (* techmap_autopurge *) to suppress techmap warnings
2019-09-19 Eddie HungD is 25 bits not 24 bits wide
2019-09-19 Eddie HungMerge remote-tracking branch 'origin/clifford/fix1381...
2019-09-19 Eddie Hungsynth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB...
2019-09-19 Eddie HungTidy up synth_ice40, only restrict DSP_B_MINWIDTH=2
2019-09-19 Marcin KościelnickiUse extractinv for synth_xilinx -ise
2019-09-18 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-09-18 Eddie HungMerge pull request #1355 from YosysHQ/eddie/peepopt_dff...
2019-09-18 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-09-18 Eddie HungFix copy-paste
2019-09-18 Eddie HungMis-spell
2019-09-18 Eddie HungAdd pattern detection support for DSP48E1 model, check...
2019-09-18 Eddie HungMerge pull request #1379 from mmicko/sim_models
2019-09-18 Miodrag Milanovicmake note that it is for latch mode
2019-09-18 Miodrag Milanovicbetter lut handling
2019-09-18 Miodrag Milanovicbetter handling of lut and begin/end add
2019-09-15 Eddie HungMerge pull request #1374 from YosysHQ/eddie/fix1371
2019-09-15 Marcin Kościelnickixilinx: Make blackbox library family-dependent.
2019-09-15 Miodrag MilanovicAdded simulation models for Efinix and Anlogic
2019-09-14 Eddie HungAdd `undef DSP48E1_INST
2019-09-13 Eddie HungFix D -> P{,COUT} delay
2019-09-13 Eddie HungAdd no MULT no DPORT config
2019-09-13 Eddie HungAdd support for MULT and DPORT
2019-09-13 Eddie HungRefine diagram
2019-09-13 Eddie HungAdd an ASCII drawing
2019-09-13 Eddie HungFinish explanation
2019-09-13 Eddie HungRename to techmap_guard
2019-09-13 Eddie HungInitial DSP48E1 box support
2019-09-13 Eddie HungSet more ports explicitly
2019-09-12 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
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