Added $alu support to test_cell
[yosys.git] / techlibs /
2014-09-01 Clifford WolfFixed "test_cell -simlib all"
2014-08-31 Clifford WolfAdded $lut support in test_cell, techmap, satgen
2014-08-30 Clifford WolfAdded $alu cell type
2014-08-30 Clifford WolfReplaced $__alu CO/CS outputs with full-width CO output
2014-08-18 Clifford WolfUsing "via_celltype" in $mul carry-save-acc implementation
2014-08-17 Clifford WolfPerformance fix for new $__lcu techmap rule
2014-08-17 Clifford WolfReplaced recursive lcu scheme with bk adder
2014-08-16 Clifford WolfMultiply using a carry-save accumulator
2014-08-16 Clifford WolfAdded additional gate types: $_NAND_ $_NOR_ $_XNOR_...
2014-08-16 Clifford WolfChanges in techmap $__alu interface
2014-08-15 Clifford WolfRenamed $lut ports to follow A-Y naming scheme
2014-08-15 Clifford WolfRenamed $_INV_ cell type to $_NOT_
2014-08-14 Clifford WolfSimplified $__arraymul techmap rule
2014-08-14 Clifford WolfRIP $safe_pmux
2014-08-13 Clifford WolfAdded techmap support for actual lookahead carry unit
2014-08-13 Clifford WolfPreparations for lookahead ALU support in techmap.v
2014-08-13 Clifford WolfNew interface for $__alu in techmap.v
2014-08-07 Clifford WolfAdded adff2dff.v (for techmap -share_map)
2014-08-03 Clifford WolfImplemented recursive techmap
2014-07-31 Clifford WolfRenamed "stdcells.v" to "techmap.v"
2014-07-31 Clifford WolfReorganized stdcells.v (no actual code change, just...
2014-07-30 Clifford WolfAdded techmap CONSTMAP feature
2014-07-30 Clifford WolfNew techmap default rules for $shr $sshr $shl $sshl
2014-07-29 Clifford WolfBugfix in simlib.v for iverilog
2014-07-29 Clifford WolfAdded $shift and $shiftx cell types (needed for correct...
2014-07-24 Clifford WolfAdded "make PRETTY=1"
2014-07-17 Clifford WolfFixed simlib.v model for $mem
2014-07-16 Clifford WolfMerged new $mem/$memwr WR_EN interface
2014-07-16 Clifford WolfUpdated simlib to new $mem/$memwr interface
2014-04-02 Clifford WolfAdded SIMLIB_NOLUT to simlib.v
2014-04-02 Clifford WolfAdded SIMLIB_NOSR to simlib.v
2014-03-31 Clifford WolfAdded support for dlatchsr cells
2014-03-11 Clifford WolfMerged addition of SED makefile variable from github...
2014-03-10 Siesh1oo - Makefile, techlibs/common/Makefile.inc: call GNU...
2014-03-06 Clifford WolfFixes for improved techmap of shifts with large B inputs
2014-03-06 Clifford WolfStrictly zero-extend unsigned A-inputs of shift operati...
2014-03-06 Clifford WolfImproved techmap of shift with wide B inputs
2014-02-07 Clifford WolfAdded $slice and $concat cell types
2014-02-03 Clifford WolfAdded TRANSPARENT parameter to $memrd (and RD_TRANSPARE...
2014-01-31 Clifford WolfMore changes to techlibs/common/simlib.v for LEC
2014-01-29 Clifford WolfAdded test comments to techlibs/cmos/cmos_cells.lib
2014-01-28 Clifford WolfMajor rewrite of techlibs/common/simlib.v for LEC ...
2014-01-20 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-19 Clifford WolfAdded $assert cell
2014-01-18 Clifford WolfFixed $lut simlib model for a wider range of tools
2014-01-18 Clifford WolfMore changes to simlib to make it friendlier to a wider...
2014-01-18 Clifford WolfFixed a type in $mem model in simlib.v
2014-01-18 Ahmed IrfanMerge branch 'master' of https://github.com/ahmedirfan1...
2014-01-18 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-18 Ahmed Irfanpmux2mux
2014-01-18 Clifford WolfRemoved cases of trailing comma in stdcells.v
2014-01-18 Clifford WolfAdded $bu0 cell to simlib.v
2014-01-17 Clifford WolfAdded techlibs/common/pmux2mux.v
2014-01-17 Ahmed IrfanMerge branch 'master' of https://github.com/ahmedirfan1...
2014-01-17 Ahmed IrfanMerge branch 'master' of https://github.com/ahmedirfan1...
2014-01-15 Ahmed IrfanMerge branch 'master' of https://github.com/ahmedirfan1...
2014-01-14 Ahmed IrfanMerge branch 'master' of https://github.com/ahmedirfan1...
2014-01-03 Ahmed Irfansplitnet -driver feature
2014-01-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-03 Ahmed Irfanbtor
2013-12-31 Clifford WolfVarious small cleanups in stdcells.v techmap code
2013-12-28 Clifford WolfAdded $bu0 cell (for easy correct $eq/$ne mapping)
2013-12-27 Clifford WolfAdded support for non-const === and !== (for miter...
2013-11-24 Clifford WolfUsing simplemap mappers from techmap
2013-11-24 Clifford WolfRenamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 Clifford WolfAdded "techmap -share_map" option
2013-11-24 Clifford WolfFixed xilinx/example_sim_counter test bench
2013-11-23 Clifford WolfAdded more generic _TECHMAP_ wire mechanism to techmap...
2013-11-21 Clifford WolfUpdated abc
2013-11-19 Clifford WolfInstall simlib in datdir
2013-11-18 Clifford WolfAdded commented-out osu025 maping commands to cmos...
2013-11-10 Clifford WolfCleanups and bugfixes in response to new internal cell...
2013-11-06 Clifford WolfFixed techmap of $reduce_xnor with multi-bit outputs
2013-11-06 Clifford WolfFixed techmap of $gt and $ge with multi-bit outputs
2013-11-06 Clifford WolfImproved width extension with regard to undef propagation
2013-11-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-10-31 Clifford WolfAdded DFFSR cell to techlibs/cmos/cmos_cells.lib
2013-10-27 Clifford WolfMerge pull request #12 from jameswalmsley/master
2013-10-27 James Walmsley[EXAMPLES] Ported the mojo counter example to Zynq...
2013-10-27 Clifford WolfCleanups in xilinx examples
2013-10-27 Clifford WolfAdded synth_xilinx command
2013-10-27 Clifford WolfMoved simple xilinx counter sim example to subdir
2013-10-27 Clifford WolfXilinx mojo_counter example is now working
2013-10-26 Clifford WolfRenamed techlibs/xilinx7 to techlibs/xilinx
2013-10-26 Clifford WolfImproved xilinx mojo_counter example
2013-10-26 Clifford WolfAdded another xilinx example (not funcional yet)
2013-10-18 Clifford WolfBugfix in dffsr techmap rules
2013-10-18 Clifford WolfAdded techmap rules for $sr, $dffsr and $dlatch
2013-10-18 Clifford WolfAdded $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_...
2013-10-18 Clifford WolfAdded $sr, $dffsr and $dlatch cell types
2013-10-16 Clifford WolfAdded map, par and bitgen to xlinx7 example
2013-09-15 Clifford WolfMoved common techlib files to techlibs/common
2013-09-14 Clifford WolfAdded spice testbench to techlibs/cmos
2013-09-14 Clifford WolfAdded spice backend
2013-09-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-08-27 Clifford WolfAdded mapping to techlibs/xilinx7 testbench (exposes...
2013-08-22 Clifford WolfAdded simple xilinx7 technology mapping files
2013-08-15 Clifford WolfImplemented same div-by-zero behavior as found in other...
2013-08-09 Clifford WolfAdded $div and $mod technology mapping
2013-07-23 Clifford WolfAdded $lut cells and abc lut mapping support
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