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Added $alu support to test_cell
[yosys.git]
/
techlibs
/
2014-09-01
Clifford Wolf
Fixed "test_cell -simlib all"
tree
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commitdiff
2014-08-31
Clifford Wolf
Added $lut support in test_cell, techmap, satgen
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commitdiff
2014-08-30
Clifford Wolf
Added $alu cell type
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commitdiff
2014-08-30
Clifford Wolf
Replaced $__alu CO/CS outputs with full-width CO output
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commitdiff
2014-08-18
Clifford Wolf
Using "via_celltype" in $mul carry-save-acc implementation
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commitdiff
2014-08-17
Clifford Wolf
Performance fix for new $__lcu techmap rule
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commitdiff
2014-08-17
Clifford Wolf
Replaced recursive lcu scheme with bk adder
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commitdiff
2014-08-16
Clifford Wolf
Multiply using a carry-save accumulator
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commitdiff
2014-08-16
Clifford Wolf
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_...
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commitdiff
2014-08-16
Clifford Wolf
Changes in techmap $__alu interface
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commitdiff
2014-08-15
Clifford Wolf
Renamed $lut ports to follow A-Y naming scheme
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commitdiff
2014-08-15
Clifford Wolf
Renamed $_INV_ cell type to $_NOT_
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commitdiff
2014-08-14
Clifford Wolf
Simplified $__arraymul techmap rule
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commitdiff
2014-08-14
Clifford Wolf
RIP $safe_pmux
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commitdiff
2014-08-13
Clifford Wolf
Added techmap support for actual lookahead carry unit
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commitdiff
2014-08-13
Clifford Wolf
Preparations for lookahead ALU support in techmap.v
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commitdiff
2014-08-13
Clifford Wolf
New interface for $__alu in techmap.v
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commitdiff
2014-08-07
Clifford Wolf
Added adff2dff.v (for techmap -share_map)
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commitdiff
2014-08-03
Clifford Wolf
Implemented recursive techmap
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commitdiff
2014-07-31
Clifford Wolf
Renamed "stdcells.v" to "techmap.v"
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commitdiff
2014-07-31
Clifford Wolf
Reorganized stdcells.v (no actual code change, just...
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commitdiff
2014-07-30
Clifford Wolf
Added techmap CONSTMAP feature
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commitdiff
2014-07-30
Clifford Wolf
New techmap default rules for $shr $sshr $shl $sshl
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commitdiff
2014-07-29
Clifford Wolf
Bugfix in simlib.v for iverilog
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commitdiff
2014-07-29
Clifford Wolf
Added $shift and $shiftx cell types (needed for correct...
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commitdiff
2014-07-24
Clifford Wolf
Added "make PRETTY=1"
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commitdiff
2014-07-17
Clifford Wolf
Fixed simlib.v model for $mem
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commitdiff
2014-07-16
Clifford Wolf
Merged new $mem/$memwr WR_EN interface
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commitdiff
2014-07-16
Clifford Wolf
Updated simlib to new $mem/$memwr interface
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commitdiff
2014-04-02
Clifford Wolf
Added SIMLIB_NOLUT to simlib.v
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commitdiff
2014-04-02
Clifford Wolf
Added SIMLIB_NOSR to simlib.v
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commitdiff
2014-03-31
Clifford Wolf
Added support for dlatchsr cells
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commitdiff
2014-03-11
Clifford Wolf
Merged addition of SED makefile variable from github...
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commitdiff
2014-03-10
Siesh1oo
- Makefile, techlibs/common/Makefile.inc: call GNU...
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commitdiff
2014-03-06
Clifford Wolf
Fixes for improved techmap of shifts with large B inputs
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commitdiff
2014-03-06
Clifford Wolf
Strictly zero-extend unsigned A-inputs of shift operati...
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commitdiff
2014-03-06
Clifford Wolf
Improved techmap of shift with wide B inputs
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commitdiff
2014-02-07
Clifford Wolf
Added $slice and $concat cell types
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commitdiff
2014-02-03
Clifford Wolf
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARE...
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commitdiff
2014-01-31
Clifford Wolf
More changes to techlibs/common/simlib.v for LEC
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commitdiff
2014-01-29
Clifford Wolf
Added test comments to techlibs/cmos/cmos_cells.lib
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commitdiff
2014-01-28
Clifford Wolf
Major rewrite of techlibs/common/simlib.v for LEC ...
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commitdiff
2014-01-20
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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commitdiff
2014-01-19
Clifford Wolf
Added $assert cell
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commitdiff
2014-01-18
Clifford Wolf
Fixed $lut simlib model for a wider range of tools
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commitdiff
2014-01-18
Clifford Wolf
More changes to simlib to make it friendlier to a wider...
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commitdiff
2014-01-18
Clifford Wolf
Fixed a type in $mem model in simlib.v
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commitdiff
2014-01-18
Ahmed Irfan
Merge branch 'master' of https://github.com/ahmedirfan1...
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commitdiff
2014-01-18
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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commitdiff
2014-01-18
Ahmed Irfan
pmux2mux
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commitdiff
2014-01-18
Clifford Wolf
Removed cases of trailing comma in stdcells.v
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commitdiff
2014-01-18
Clifford Wolf
Added $bu0 cell to simlib.v
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commitdiff
2014-01-17
Clifford Wolf
Added techlibs/common/pmux2mux.v
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commitdiff
2014-01-17
Ahmed Irfan
Merge branch 'master' of https://github.com/ahmedirfan1...
tree
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commitdiff
2014-01-17
Ahmed Irfan
Merge branch 'master' of https://github.com/ahmedirfan1...
tree
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commitdiff
2014-01-15
Ahmed Irfan
Merge branch 'master' of https://github.com/ahmedirfan1...
tree
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commitdiff
2014-01-14
Ahmed Irfan
Merge branch 'master' of https://github.com/ahmedirfan1...
tree
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commitdiff
2014-01-03
Ahmed Irfan
splitnet -driver feature
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commitdiff
2014-01-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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commitdiff
2014-01-03
Ahmed Irfan
btor
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commitdiff
2013-12-31
Clifford Wolf
Various small cleanups in stdcells.v techmap code
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commitdiff
2013-12-28
Clifford Wolf
Added $bu0 cell (for easy correct $eq/$ne mapping)
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commitdiff
2013-12-27
Clifford Wolf
Added support for non-const === and !== (for miter...
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commitdiff
2013-11-24
Clifford Wolf
Using simplemap mappers from techmap
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commitdiff
2013-11-24
Clifford Wolf
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
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commitdiff
2013-11-24
Clifford Wolf
Added "techmap -share_map" option
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commitdiff
2013-11-24
Clifford Wolf
Fixed xilinx/example_sim_counter test bench
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commitdiff
2013-11-23
Clifford Wolf
Added more generic _TECHMAP_ wire mechanism to techmap...
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commitdiff
2013-11-21
Clifford Wolf
Updated abc
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commitdiff
2013-11-19
Clifford Wolf
Install simlib in datdir
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commitdiff
2013-11-18
Clifford Wolf
Added commented-out osu025 maping commands to cmos...
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commitdiff
2013-11-10
Clifford Wolf
Cleanups and bugfixes in response to new internal cell...
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commitdiff
2013-11-06
Clifford Wolf
Fixed techmap of $reduce_xnor with multi-bit outputs
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commitdiff
2013-11-06
Clifford Wolf
Fixed techmap of $gt and $ge with multi-bit outputs
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commitdiff
2013-11-06
Clifford Wolf
Improved width extension with regard to undef propagation
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commitdiff
2013-11-03
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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commitdiff
2013-10-31
Clifford Wolf
Added DFFSR cell to techlibs/cmos/cmos_cells.lib
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commitdiff
2013-10-27
Clifford Wolf
Merge pull request #12 from jameswalmsley/master
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commitdiff
2013-10-27
James Walmsley
[EXAMPLES] Ported the mojo counter example to Zynq...
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commitdiff
2013-10-27
Clifford Wolf
Cleanups in xilinx examples
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commitdiff
2013-10-27
Clifford Wolf
Added synth_xilinx command
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commitdiff
2013-10-27
Clifford Wolf
Moved simple xilinx counter sim example to subdir
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commitdiff
2013-10-27
Clifford Wolf
Xilinx mojo_counter example is now working
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commitdiff
2013-10-26
Clifford Wolf
Renamed techlibs/xilinx7 to techlibs/xilinx
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commitdiff
2013-10-26
Clifford Wolf
Improved xilinx mojo_counter example
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commitdiff
2013-10-26
Clifford Wolf
Added another xilinx example (not funcional yet)
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commitdiff
2013-10-18
Clifford Wolf
Bugfix in dffsr techmap rules
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commitdiff
2013-10-18
Clifford Wolf
Added techmap rules for $sr, $dffsr and $dlatch
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commitdiff
2013-10-18
Clifford Wolf
Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_...
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commitdiff
2013-10-18
Clifford Wolf
Added $sr, $dffsr and $dlatch cell types
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commitdiff
2013-10-16
Clifford Wolf
Added map, par and bitgen to xlinx7 example
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commitdiff
2013-09-15
Clifford Wolf
Moved common techlib files to techlibs/common
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commitdiff
2013-09-14
Clifford Wolf
Added spice testbench to techlibs/cmos
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commitdiff
2013-09-14
Clifford Wolf
Added spice backend
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commitdiff
2013-09-03
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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commitdiff
2013-08-27
Clifford Wolf
Added mapping to techlibs/xilinx7 testbench (exposes...
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commitdiff
2013-08-22
Clifford Wolf
Added simple xilinx7 technology mapping files
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commitdiff
2013-08-15
Clifford Wolf
Implemented same div-by-zero behavior as found in other...
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commitdiff
2013-08-09
Clifford Wolf
Added $div and $mod technology mapping
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commitdiff
2013-07-23
Clifford Wolf
Added $lut cells and abc lut mapping support
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