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abc9 to do clock partitioning again
[yosys.git]
/
techlibs
/
2019-12-06
Eddie Hung
Remove clkpart
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commitdiff
2019-12-05
Eddie Hung
Revert "Special abc9_clock wire to contain only clock...
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commitdiff
2019-12-05
Eddie Hung
Missing wire declaration
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commitdiff
2019-12-05
Eddie Hung
abc9_map.v to transform INIT=1 to INIT=0
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commitdiff
2019-12-05
Eddie Hung
Oh deary me
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commitdiff
2019-12-05
Eddie Hung
output reg Q -> output Q to suppress warning
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commitdiff
2019-12-05
Eddie Hung
abc9_map.v to do `zinit' and make INIT = 1'b0
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commitdiff
2019-12-04
Eddie Hung
Add abc9_init wire, attach to abc9_flop cell
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commitdiff
2019-12-03
Eddie Hung
Revert "Add INIT value to abc9_control"
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commitdiff
2019-12-03
Eddie Hung
techmap abc_unmap.v before xilinx_srl -fixed
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commitdiff
2019-12-02
Eddie Hung
Add INIT value to abc9_control
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commitdiff
2019-11-28
Eddie Hung
clkpart -unpart into 'finalize'
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commitdiff
2019-11-28
Eddie Hung
Merge remote-tracking branch 'origin/eddie/submod_po...
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commitdiff
2019-11-27
Eddie Hung
Merge remote-tracking branch 'origin/eddie/submod_po...
tree
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commitdiff
2019-11-27
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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commitdiff
2019-11-27
Eddie Hung
ean call after abc{,9}
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commitdiff
2019-11-27
Eddie Hung
Merge remote-tracking branch 'origin/eddie/submod_po...
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commitdiff
2019-11-27
Clifford Wolf
Merge pull request #1501 from YosysHQ/dave/mem_copy_attr
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commitdiff
2019-11-27
Eddie Hung
Merge remote-tracking branch 'origin/eddie/write_xaiger...
tree
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commitdiff
2019-11-27
Eddie Hung
Merge remote-tracking branch 'origin/eddie/clkpart...
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commitdiff
2019-11-27
Eddie Hung
Merge remote-tracking branch 'origin/eddie/submod_po...
tree
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commitdiff
2019-11-27
Eddie Hung
Merge branch 'master' into xaig_dff
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commitdiff
2019-11-26
Eddie Hung
Move 'clean' from map_luts to finalize
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commitdiff
2019-11-26
Marcin Kościelnicki
xilinx: Add simulation models for IOBUF and OBUFT.
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commitdiff
2019-11-25
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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commitdiff
2019-11-25
Eddie Hung
Special abc9_clock wire to contain only clock signal
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commitdiff
2019-11-25
Marcin Kościelnicki
clkbufmap: Add support for inverters in clock path.
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commitdiff
2019-11-25
Marcin Kościelnicki
xilinx: Use INV instead of LUT1 when applicable
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commitdiff
2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/clkpart...
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commitdiff
2019-11-23
Eddie Hung
For abc9, run clkpart before ff_map and after abc9
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commitdiff
2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/clkpart...
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commitdiff
2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/clkpart...
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commitdiff
2019-11-23
Eddie Hung
Merge branch 'xaig_dff' of github.com:YosysHQ/yosys...
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commitdiff
2019-11-23
Eddie Hung
Merge pull request #1505 from YosysHQ/eddie/xaig_dff_adff
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commitdiff
2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/clkpart...
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commitdiff
2019-11-23
Eddie Hung
Merge pull request #1520 from pietrmar/fix-1463
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commitdiff
2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/submod_po...
tree
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commitdiff
2019-11-23
Martin Pietryka
coolrunner2: remove spurious log_pop() call, fixes...
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commitdiff
2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/submod_po...
tree
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commitdiff
2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/submod_po...
tree
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commitdiff
2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/clkpart...
tree
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commitdiff
2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/submod_po...
tree
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commitdiff
2019-11-22
Eddie Hung
Merge branch 'eddie/clkpart' into xaig_dff
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commitdiff
2019-11-22
Eddie Hung
Merge branch 'eddie/clkpart' into xaig_dff
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commitdiff
2019-11-22
Eddie Hung
Merge branch 'master' of github.com:YosysHQ/yosys
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commitdiff
2019-11-22
Clifford Wolf
Merge pull request #1511 from YosysHQ/dave/always
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commitdiff
2019-11-22
Marcin Kościelnicki
gowin: Add missing .gitignore entries
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commitdiff
2019-11-22
Eddie Hung
Merge remote-tracking branch 'origin/xaig_dff' into...
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commitdiff
2019-11-22
Eddie Hung
Merge branch 'eddie/xaig_dff_adff' into xaig_dff
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commitdiff
2019-11-20
Eddie Hung
Add blackbox model for $__ABC9_FF_ so that clock partit...
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commitdiff
2019-11-20
Eddie Hung
Fix INIT values
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commitdiff
2019-11-20
Eddie Hung
Do not drop async control signals in abc_map.v
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commitdiff
2019-11-19
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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commitdiff
2019-11-19
Clifford Wolf
Merge pull request #1449 from pepijndevos/gowin
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commitdiff
2019-11-19
Pepijn de Vos
Remove dff init altogether
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commitdiff
2019-11-19
Marcin Kościelnicki
xilinx: Add simulation models for MULT18X18* and DSP48A*.
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commitdiff
2019-11-18
Pepijn de Vos
add help for nowidelut and abc9 options
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commitdiff
2019-11-18
whitequark
Merge pull request #1494 from whitequark/write_verilog...
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commitdiff
2019-11-17
Clifford Wolf
Merge pull request #1492 from YosysHQ/dave/wreduce...
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commitdiff
2019-11-16
Pepijn de Vos
Merge branch 'master' of https://github.com/YosysHQ...
tree
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commitdiff
2019-11-15
David Shah
ecp5: Use new autoname pass for better cell/net names
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commitdiff
2019-11-14
Clifford Wolf
Merge pull request #1490 from YosysHQ/clifford/autoname
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commitdiff
2019-11-14
Clifford Wolf
Merge pull request #1444 from btut/feature/python_wrapp...
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commitdiff
2019-11-14
Clifford Wolf
Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim
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commitdiff
2019-11-14
Clifford Wolf
Merge branch 'label-bads-btor' of https://github.com...
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commitdiff
2019-11-13
Clifford Wolf
Add "autoname" pass and use it in "synth_ice40"
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commitdiff
2019-11-13
whitequark
Merge pull request #1488 from whitequark/flowmap-fixes
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commitdiff
2019-11-12
Clifford Wolf
Merge pull request #1484 from YosysHQ/clifford/cmp2luteqne
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commitdiff
2019-11-11
Pepijn de Vos
fix fsm test with proper clock enable polarity
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commitdiff
2019-11-11
Pepijn de Vos
Merge branch 'master' of https://github.com/YosysHQ...
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commitdiff
2019-11-11
Clifford Wolf
Do not map $eq and $ne in cmp2lut, only proper arithmet...
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commitdiff
2019-11-10
Clifford Wolf
Merge pull request #1470 from YosysHQ/clifford/subpassdoc
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commitdiff
2019-11-06
Pepijn de Vos
fix wide luts
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commitdiff
2019-11-06
Marcin Kościelnicki
synth_xilinx: Merge blackbox primitive libraries.
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commitdiff
2019-10-28
Pepijn de Vos
add IOBUF
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commitdiff
2019-10-28
Pepijn de Vos
add tristate buffer and test
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commitdiff
2019-10-28
Pepijn de Vos
More formatting
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commitdiff
2019-10-28
Pepijn de Vos
really really fix formatting maybe
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commitdiff
2019-10-28
Pepijn de Vos
undo formatting fuckup
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commitdiff
2019-10-28
Pepijn de Vos
add wide luts
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commitdiff
2019-10-28
Pepijn de Vos
add 32-bit BRAM and byte-enables
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commitdiff
2019-10-27
Clifford Wolf
Merge pull request #1393 from whitequark/write_verilog...
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commitdiff
2019-10-24
Pepijn de Vos
ALU sim tweaks
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commitdiff
2019-10-24
David Shah
Merge pull request #1455 from YosysHQ/dave/ultrascaleplus
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commitdiff
2019-10-23
David Shah
ice40: Add post-pnr ICESTORM_RAM model and fix FFs
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commitdiff
2019-10-23
David Shah
ice40: Support for post-pnr timing simulation
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commitdiff
2019-10-23
David Shah
xilinx: Add URAM288 mapping for xcup
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commitdiff
2019-10-23
David Shah
xilinx: Add support for UltraScale[+] BRAM mapping
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commitdiff
2019-10-22
Marcin Kościelnicki
xilinx: Support multiplier mapping for all families.
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commitdiff
2019-10-22
Clifford Wolf
Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg
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commitdiff
2019-10-21
Pepijn de Vos
add a few more missing dff
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commitdiff
2019-10-21
Pepijn de Vos
add negedge DFF
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commitdiff
2019-10-21
Pepijn de Vos
use ADDSUB ALU mode to remove inverters
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commitdiff
2019-10-21
Pepijn de Vos
Merge branch 'master' of https://github.com/YosysHQ...
tree
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commitdiff
2019-10-20
David Shah
ecp5: Pass -nomfs to abc9
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commitdiff
2019-10-19
Miodrag Milanović
Merge pull request #1457 from xobs/python-binary-name
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commitdiff
2019-10-19
Sean Cross
Makefile: don't assume python is called `python3`
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commitdiff
2019-10-18
Miodrag Milanović
Merge pull request #1435 from YosysHQ/mmicko/efinix
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commitdiff
2019-10-18
Miodrag Milanović
Merge branch 'master' into mmicko/efinix
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commitdiff
2019-10-18
Miodrag Milanović
Merge branch 'master' into mmicko/anlogic
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