Remove clkpart
[yosys.git] / techlibs /
2019-12-06 Eddie HungRemove clkpart
2019-12-05 Eddie HungRevert "Special abc9_clock wire to contain only clock...
2019-12-05 Eddie HungMissing wire declaration
2019-12-05 Eddie Hungabc9_map.v to transform INIT=1 to INIT=0
2019-12-05 Eddie HungOh deary me
2019-12-05 Eddie Hungoutput reg Q -> output Q to suppress warning
2019-12-05 Eddie Hungabc9_map.v to do `zinit' and make INIT = 1'b0
2019-12-04 Eddie HungAdd abc9_init wire, attach to abc9_flop cell
2019-12-03 Eddie HungRevert "Add INIT value to abc9_control"
2019-12-03 Eddie Hungtechmap abc_unmap.v before xilinx_srl -fixed
2019-12-02 Eddie HungAdd INIT value to abc9_control
2019-11-28 Eddie Hungclkpart -unpart into 'finalize'
2019-11-28 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-11-27 Eddie Hungean call after abc{,9}
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-27 Clifford WolfMerge pull request #1501 from YosysHQ/dave/mem_copy_attr
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/write_xaiger...
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-27 Eddie HungMerge branch 'master' into xaig_dff
2019-11-26 Eddie HungMove 'clean' from map_luts to finalize
2019-11-26 Marcin Kościelnickixilinx: Add simulation models for IOBUF and OBUFT.
2019-11-25 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-11-25 Eddie HungSpecial abc9_clock wire to contain only clock signal
2019-11-25 Marcin Kościelnickiclkbufmap: Add support for inverters in clock path.
2019-11-25 Marcin Kościelnickixilinx: Use INV instead of LUT1 when applicable
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungFor abc9, run clkpart before ff_map and after abc9
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungMerge branch 'xaig_dff' of github.com:YosysHQ/yosys...
2019-11-23 Eddie HungMerge pull request #1505 from YosysHQ/eddie/xaig_dff_adff
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungMerge pull request #1520 from pietrmar/fix-1463
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-23 Martin Pietrykacoolrunner2: remove spurious log_pop() call, fixes...
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-22 Eddie HungMerge branch 'eddie/clkpart' into xaig_dff
2019-11-22 Eddie HungMerge branch 'eddie/clkpart' into xaig_dff
2019-11-22 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-11-22 Clifford WolfMerge pull request #1511 from YosysHQ/dave/always
2019-11-22 Marcin Kościelnickigowin: Add missing .gitignore entries
2019-11-22 Eddie HungMerge remote-tracking branch 'origin/xaig_dff' into...
2019-11-22 Eddie HungMerge branch 'eddie/xaig_dff_adff' into xaig_dff
2019-11-20 Eddie HungAdd blackbox model for $__ABC9_FF_ so that clock partit...
2019-11-20 Eddie HungFix INIT values
2019-11-20 Eddie HungDo not drop async control signals in abc_map.v
2019-11-19 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-11-19 Clifford WolfMerge pull request #1449 from pepijndevos/gowin
2019-11-19 Pepijn de VosRemove dff init altogether
2019-11-19 Marcin Kościelnickixilinx: Add simulation models for MULT18X18* and DSP48A*.
2019-11-18 Pepijn de Vosadd help for nowidelut and abc9 options
2019-11-18 whitequarkMerge pull request #1494 from whitequark/write_verilog...
2019-11-17 Clifford WolfMerge pull request #1492 from YosysHQ/dave/wreduce...
2019-11-16 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-11-15 David Shahecp5: Use new autoname pass for better cell/net names
2019-11-14 Clifford WolfMerge pull request #1490 from YosysHQ/clifford/autoname
2019-11-14 Clifford WolfMerge pull request #1444 from btut/feature/python_wrapp...
2019-11-14 Clifford WolfMerge pull request #1465 from YosysHQ/dave/ice40_timing_sim
2019-11-14 Clifford WolfMerge branch 'label-bads-btor' of https://github.com...
2019-11-13 Clifford WolfAdd "autoname" pass and use it in "synth_ice40"
2019-11-13 whitequarkMerge pull request #1488 from whitequark/flowmap-fixes
2019-11-12 Clifford WolfMerge pull request #1484 from YosysHQ/clifford/cmp2luteqne
2019-11-11 Pepijn de Vosfix fsm test with proper clock enable polarity
2019-11-11 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-11-11 Clifford WolfDo not map $eq and $ne in cmp2lut, only proper arithmet...
2019-11-10 Clifford WolfMerge pull request #1470 from YosysHQ/clifford/subpassdoc
2019-11-06 Pepijn de Vosfix wide luts
2019-11-06 Marcin Kościelnickisynth_xilinx: Merge blackbox primitive libraries.
2019-10-28 Pepijn de Vosadd IOBUF
2019-10-28 Pepijn de Vosadd tristate buffer and test
2019-10-28 Pepijn de VosMore formatting
2019-10-28 Pepijn de Vosreally really fix formatting maybe
2019-10-28 Pepijn de Vosundo formatting fuckup
2019-10-28 Pepijn de Vosadd wide luts
2019-10-28 Pepijn de Vosadd 32-bit BRAM and byte-enables
2019-10-27 Clifford WolfMerge pull request #1393 from whitequark/write_verilog...
2019-10-24 Pepijn de VosALU sim tweaks
2019-10-24 David ShahMerge pull request #1455 from YosysHQ/dave/ultrascaleplus
2019-10-23 David Shahice40: Add post-pnr ICESTORM_RAM model and fix FFs
2019-10-23 David Shahice40: Support for post-pnr timing simulation
2019-10-23 David Shahxilinx: Add URAM288 mapping for xcup
2019-10-23 David Shahxilinx: Add support for UltraScale[+] BRAM mapping
2019-10-22 Marcin Kościelnickixilinx: Support multiplier mapping for all families.
2019-10-22 Clifford WolfMerge pull request #1452 from nakengelhardt/fix_dsp_mem_reg
2019-10-21 Pepijn de Vosadd a few more missing dff
2019-10-21 Pepijn de Vosadd negedge DFF
2019-10-21 Pepijn de Vosuse ADDSUB ALU mode to remove inverters
2019-10-21 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-10-20 David Shahecp5: Pass -nomfs to abc9
2019-10-19 Miodrag MilanovićMerge pull request #1457 from xobs/python-binary-name
2019-10-19 Sean CrossMakefile: don't assume python is called `python3`
2019-10-18 Miodrag MilanovićMerge pull request #1435 from YosysHQ/mmicko/efinix
2019-10-18 Miodrag MilanovićMerge branch 'master' into mmicko/efinix
2019-10-18 Miodrag MilanovićMerge branch 'master' into mmicko/anlogic
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