Merge https://github.com/YosysHQ/yosys into xaig
[yosys.git] / techlibs /
2019-02-13 Eddie HungMerge https://github.com/YosysHQ/yosys into xaig
2019-02-06 Eddie HungMerge branch 'dff_init' of https://github.com/eddiehung...
2019-02-06 Eddie HungAdd INIT parameter to all ff/latch cells
2019-01-27 Clifford WolfMerge pull request #798 from mmicko/master
2019-01-25 Miodrag MilanovicFixed Anlogic simulation model
2019-01-17 Clifford WolfAdd SF2 IO buffer insertion
2019-01-17 Clifford WolfAdd "synth_sf2 -vlog", fix "synth_sf2 -edif"
2019-01-07 Clifford WolfMerge pull request #782 from whitequark/flowmap_dfs
2019-01-04 Clifford WolfMerge pull request #777 from mmicko/achronix_cell_sim_fix
2019-01-04 Miodrag MilanovicFix cells_sim.v for Achronix FPGA
2019-01-04 Clifford WolfMerge pull request #776 from mmicko/unify_noflatten
2019-01-04 Miodrag MilanovicUnify usage of noflatten among architectures
2019-01-02 Clifford WolfMerge pull request #770 from whitequark/opt_expr_cmp
2019-01-02 Clifford WolfMerge pull request #755 from Icenowy/anlogic-dram-init
2019-01-02 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys
2019-01-02 Clifford WolfMerge pull request #750 from Icenowy/anlogic-ff-init
2019-01-02 Clifford WolfMerge pull request #773 from whitequark/opt_lut_elim_fixes
2019-01-02 Clifford WolfMerge pull request #772 from whitequark/synth_lut
2019-01-02 Clifford WolfMerge pull request #771 from whitequark/techmap_cmp2lut
2019-01-02 Clifford WolfMerge pull request #769 from whitequark/typos
2019-01-02 whitequarkFix typographical and grammatical errors and inconsiste...
2019-01-02 whitequarksynth_ice40: use 4-LUT coarse synthesis mode.
2019-01-02 whitequarksynth: add k-LUT mode.
2019-01-02 whitequarksynth: improve script documentation. NFC.
2019-01-02 whitequarkcmp2lut: new techmap pass.
2018-12-31 Clifford WolfMerge pull request #766 from Icenowy/anlogic-latches
2018-12-29 Larry DoolittleFix 7 instances of add_share_file to add_gen_share_file
2018-12-25 Icenowy Zhenganlogic: add latch cells
2018-12-23 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys
2018-12-22 Clifford WolfMerge pull request #757 from whitequark/manual_mem
2018-12-19 Icenowy Zhenganlogic: implement DRAM initialization
2018-12-19 Clifford WolfMerge pull request #752 from Icenowy/anlogic-lut-cost
2018-12-19 Clifford WolfMerge pull request #753 from Icenowy/anlogic-makefile-fix
2018-12-19 Clifford WolfMerge pull request #749 from Icenowy/anlogic-dram-fix
2018-12-19 Icenowy Zhenganlogic: fix Makefile.inc
2018-12-19 Icenowy ZhengAnlogic: let LUT5/6 have more cost than LUT4-
2018-12-18 Icenowy Zhenganlogic: set the init value of DFFs
2018-12-18 Icenowy Zhenganlogic: fix dbits of Anlogic Eagle DRAM16X4
2018-12-17 Clifford WolfMerge pull request #746 from Icenowy/anlogic-dram
2018-12-17 Icenowy Zhenganlogic: add support for Eagle Distributed RAM
2018-12-17 Icenowy ZhengRevert "Leave only real black box cells"
2018-12-16 Clifford WolfMerge pull request #736 from whitequark/select_assert_list
2018-12-16 Clifford WolfRename "fine:" label to "map:" in "synth_ice40"
2018-12-16 Clifford WolfMerge pull request #704 from webhat/feature/fix-awk
2018-12-16 Clifford WolfMerge pull request #738 from smunaut/issue_737
2018-12-16 Clifford WolfMerge pull request #735 from daveshah1/trifixes
2018-12-16 Clifford WolfMerge pull request #724 from whitequark/equiv_opt
2018-12-16 Clifford WolfMerge pull request #734 from grahamedgecombe/fix-shuffl...
2018-12-16 Clifford WolfMerge pull request #730 from smunaut/ffssr_dont_touch
2018-12-16 Clifford WolfMerge pull request #729 from whitequark/write_verilog_i...
2018-12-16 Clifford WolfMerge pull request #725 from olofk/ram4k-init
2018-12-16 Clifford WolfMerge pull request #714 from daveshah1/abc_preserve_naming
2018-12-16 Clifford WolfMerge pull request #723 from whitequark/synth_ice40_map...
2018-12-08 Sylvain Munautice40: Honor the "dont_touch" attribute in FFSSR pass
2018-12-07 whitequarkequiv_opt: pass -D EQUIV when techmapping.
2018-12-06 Olof KindgrenOnly use non-blocking assignments of SB_RAM40_4K for...
2018-12-06 whitequarksynth_ice40: split `map_gates` off `fine`.
2018-12-05 Clifford WolfMerge pull request #709 from smunaut/issue_708
2018-12-05 Clifford WolfMerge pull request #718 from whitequark/gate2lut
2018-12-05 whitequarksynth_ice40: add -noabc option, to use built-in LUT...
2018-12-05 whitequarkgate2lut: new techlib, for converting Yosys gates to...
2018-12-05 whitequarkFix typo.
2018-12-05 Clifford WolfMerge pull request #713 from Diego-HR/master
2018-12-05 Clifford WolfMerge pull request #712 from mmicko/anlogic-support
2018-12-05 Clifford WolfMerge pull request #717 from whitequark/opt_lut
2018-12-05 Clifford WolfMerge pull request #716 from whitequark/ice40_unlut
2018-12-05 whitequarkopt_lut: add -dlogic, to avoid disturbing logic such...
2018-12-05 whitequarksynth_ice40: add -relut option, to run ice40_unlut...
2018-12-05 whitequarkExtract ice40_unlut pass from ice40_opt.
2018-12-04 Clifford WolfMerge pull request #702 from smunaut/min_ce_use
2018-12-04 Diego HChanges in GoWin synth commands and ALU primitive support
2018-12-02 Miodrag MilanovicLeave only real black box cells
2018-12-01 Miodrag MilanovicInitial support for Anlogic FPGA
2018-12-01 Clifford WolfMerge pull request #676 from rafaeltp/master
2018-11-27 Sylvain Munautice40: Add option to only use CE if it'd be use by...
2018-11-12 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys
2018-11-12 Clifford WolfMerge pull request #697 from eddiehung/xilinx_ps7
2018-11-12 Clifford WolfMerge pull request #695 from daveshah1/ecp5_bb
2018-11-10 Eddie HungAdd support for Xilinx PS7 block
2018-11-09 David Shahecp5: Add 'fake' DCU parameters
2018-11-09 David Shahecp5: Add blackboxes for ancillary DCU cells
2018-11-07 David Shahecp5: Adding some blackbox cells
2018-10-31 Clifford WolfMerge branch 'igloo2'
2018-10-31 Clifford WolfFix sf2 LUT interface
2018-10-31 Clifford WolfBasic SmartFusion2 and IGLOO2 synthesis support
2018-10-25 Clifford WolfMerge pull request #678 from whentze/master
2018-10-25 Clifford WolfMerge pull request #679 from udif/pr_syntax_error
2018-10-23 Clifford WolfMerge pull request #677 from daveshah1/ecp5_dsp
2018-10-22 David Shahecp5: Remove DSP parameters that don't work
2018-10-21 David Shahecp5: Add DSP blackboxes
2018-10-21 rafaeltpMerge pull request #1 from YosysHQ/master
2018-10-19 Clifford WolfMerge pull request #673 from daveshah1/ecp5_improve
2018-10-19 David Shahecp5: Sim model fixes
2018-10-19 David Shahecp5: Add latch inference
2018-10-19 Clifford WolfMerge pull request #672 from daveshah1/fix_bram
2018-10-18 Clifford WolfMerge pull request #659 from rubund/sv_interfaces
2018-10-18 Clifford WolfMerge pull request #657 from mithro/xilinx-vpr
2018-10-18 Clifford WolfMerge pull request #664 from tklam/ignore-verilog-protect
2018-10-17 Clifford WolfMerge pull request #660 from tklam/parse-liberty-detect...
2018-10-17 Clifford WolfMerge pull request #663 from aman-goel/master
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