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Fix handling of warning and error messages within log_make_debug-blocks
[yosys.git] / techlibs /
2019-04-04 Eddie HungMerge branch 'map_cells_before_map_luts' into xc7srl tree | commitdiff
2019-04-04 Eddie Hungsynth_xilinx to map_cells before map_luts tree | commitdiff
2019-04-04 Eddie HungCleanup comments tree | commitdiff
2019-04-04 Eddie Hungt:$dff* -> t:$dff t:$dffe tree | commitdiff
2019-04-03 Eddie Hung-nosrl meant when -nobram tree | commitdiff
2019-04-03 Eddie HungRemove duplicate STARTUPE2 tree | commitdiff
2019-04-03 Eddie HungDisable shregmap in synth_xilinx if -retime tree | commitdiff
2019-04-03 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl tree | commitdiff
2019-04-02 Miodrag MilanovicMake nobram false by default for gowin tree | commitdiff
2019-04-01 Jim LawsonMerge remote-tracking branch 'upstream/master' tree | commitdiff
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu... tree | commitdiff
2019-03-25 Eddie Hungsynth_xilinx to use shregmap with -minlen 3 tree | commitdiff
2019-03-25 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl tree | commitdiff
2019-03-22 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl tree | commitdiff
2019-03-22 Clifford WolfMerge pull request #889 from YosysHQ/clifford/fix888 tree | commitdiff
2019-03-22 Clifford WolfMerge pull request #890 from YosysHQ/clifford/fix887 tree | commitdiff
2019-03-22 David ShahMerge pull request #891 from YosysHQ/xilinx_keep tree | commitdiff
2019-03-22 David Shahxilinx: Add keep attribute where appropriate tree | commitdiff
2019-03-21 Eddie HungAdd '-nosrl' option to synth_xilinx tree | commitdiff
2019-03-20 Eddie HungFine tune cells_map.v tree | commitdiff
2019-03-20 Eddie HungRevert $__SHREG_ to orig; use $__XILINX_SHREG for varia... tree | commitdiff
2019-03-20 Eddie HungAdd support for variable length Xilinx SRL > 128 tree | commitdiff
2019-03-19 Eddie HungRestore original synth_xilinx commands tree | commitdiff
2019-03-19 Eddie HungFix spacing tree | commitdiff
2019-03-19 Eddie HungFix INIT for variable length SRs that have been bumped... tree | commitdiff
2019-03-19 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl tree | commitdiff
2019-03-19 Clifford WolfMerge pull request #885 from YosysHQ/clifford/fix873 tree | commitdiff
2019-03-19 Clifford WolfAdd Xilinx negedge FFs to synth_xilinx dffinit call... tree | commitdiff
2019-03-19 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger tree | commitdiff
2019-03-16 Eddie HungOnly accept <128 for variable length, only if $shiftx... tree | commitdiff
2019-03-16 Eddie HungCleanup synth_xilinx tree | commitdiff
2019-03-16 Eddie HungWorking tree | commitdiff
2019-03-14 Eddie HungReverse bits in INIT parameter for Xilinx, since MSB... tree | commitdiff
2019-03-14 Eddie HungMisspell tree | commitdiff
2019-03-14 Eddie HungRevert "Add shregmap -init_msb_first and use in synth_x... tree | commitdiff
2019-03-14 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl tree | commitdiff
2019-03-14 Clifford WolfMerge pull request #869 from cr1901/win-shell tree | commitdiff
2019-03-14 Eddie HungAdd shregmap -init_msb_first and use in synth_xilinx tree | commitdiff
2019-03-14 Eddie HungFix cells_map for SRL tree | commitdiff
2019-03-14 Eddie HungMove shregmap until after first techmap tree | commitdiff
2019-03-13 Eddie HungRefactor $__SHREG__ in cells_map.v tree | commitdiff
2019-03-13 Clifford WolfMerge pull request #868 from YosysHQ/clifford/fixmem tree | commitdiff
2019-03-12 Clifford WolfRemove ice40/cells_sim.v hack to avoid warning for... tree | commitdiff
2019-03-09 Clifford WolfFix typo in ice40_braminit help msg tree | commitdiff
2019-03-09 Clifford WolfMerge pull request #859 from smunaut/ice40_braminit tree | commitdiff
2019-03-07 Sylvain Munautice40: Run ice40_braminit pass by default tree | commitdiff
2019-03-07 Sylvain Munautice40: Add ice40_braminit pass to allow initialization... tree | commitdiff
2019-03-07 Clifford WolfMerge pull request #856 from kprasadvnsi/master tree | commitdiff
2019-03-07 Clifford WolfAdd link to SF2 / igloo2 macro library guide tree | commitdiff
2019-03-07 Clifford WolfImprovements in sf2 cells_sim.v tree | commitdiff
2019-03-06 Clifford WolfAdd sf2 techmap rules for more FF types tree | commitdiff
2019-03-06 Clifford WolfRefactor SF2 iobuf insertion, Add clkint insertion tree | commitdiff
2019-03-06 Clifford WolfImprovements in SF2 flow and demo tree | commitdiff
2019-03-05 Clifford WolfMerge pull request #842 from litghost/merge_upstream tree | commitdiff
2019-03-05 Clifford WolfMerge pull request #850 from daveshah1/ecp5_warn_conflict tree | commitdiff
2019-03-05 Clifford WolfMerge pull request #851 from kprasadvnsi/master tree | commitdiff
2019-03-05 Clifford WolfMerge pull request #852 from ucb-bar/firrtlfixes tree | commitdiff
2019-03-05 Clifford WolfUse "write_edif -pvector bra" for Xilinx EDIF files tree | commitdiff
2019-03-04 Jim LawsonMerge remote-tracking branch 'upstream/master' tree | commitdiff
2019-03-04 Keith RothmanRevert BRAM WRITE_MODE changes. tree | commitdiff
2019-03-04 David Shahecp5: Demote conflicting FF init values to a warning tree | commitdiff
2019-03-01 Keith RothmanRevert FF models to include IS_x_INVERTED parameters. tree | commitdiff
2019-03-01 Keith RothmanUse singular for disabling of DRAM or BRAM inference. tree | commitdiff
2019-03-01 Keith RothmanModify arguments to match existing style. tree | commitdiff
2019-03-01 Keith RothmanChanges required for VPR place and route synth_xilinx. tree | commitdiff
2019-03-01 Clifford WolfMerge pull request #841 from mmicko/master tree | commitdiff
2019-03-01 Jim LawsonMerge remote-tracking branch 'upstream/master' tree | commitdiff
2019-03-01 Miodrag MilanovicFix ECP5 cells_sim for iverilog tree | commitdiff
2019-03-01 Clifford WolfMerge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode tree | commitdiff
2019-03-01 Elmsice40: use 2 bits for READ/WRITE MODE for SB_RAM map tree | commitdiff
2019-02-28 Larry DoolittleReduce amount of trailing whitespace in code base tree | commitdiff
2019-02-28 Clifford WolfMerge pull request #794 from daveshah1/ecp5improve tree | commitdiff
2019-02-28 Clifford WolfMerge pull request #827 from ucb-bar/firrtlfixes tree | commitdiff
2019-02-28 Eddie HungRemove SRL16/32 from cells_xtra tree | commitdiff
2019-02-28 Eddie HungAdd SRL16 and SRL32 sim models tree | commitdiff
2019-02-28 Eddie HungFix SRL16/32 techmap off-by-one tree | commitdiff
2019-02-28 Eddie Hungsynth_xilinx to call shregmap with enable support tree | commitdiff
2019-02-28 Eddie Hungsynth_xilinx to use shregmap with -params too tree | commitdiff
2019-02-28 Eddie Hungsynth_xilinx to now have shregmap call after dff2dffe tree | commitdiff
2019-02-28 Eddie HungAdd techmap rule for $__SHREG_DFF_P_ to SRL16/32 tree | commitdiff
2019-02-26 Larry Doolittletechlibs/greenpak4/cells_map.v: Harmonize whitespace... tree | commitdiff
2019-02-26 Larry DoolittleClean up some whitepsace outliers tree | commitdiff
2019-02-26 Jim LawsonMerge remote-tracking branch 'upstream/master' tree | commitdiff
2019-02-25 David Shahecp5: Compatibility with Migen AsyncResetSynchronizer tree | commitdiff
2019-02-24 Clifford WolfMerge pull request #812 from ucb-bar/arrayhierarchyfixes tree | commitdiff
2019-02-24 Clifford WolfMerge pull request #824 from litghost/fix_reduce_on_ff tree | commitdiff
2019-02-22 Clifford WolfMerge pull request #819 from YosysHQ/clifford/optd tree | commitdiff
2019-02-22 Clifford WolfMerge pull request #820 from YosysHQ/clifford/fix810 tree | commitdiff
2019-02-22 Clifford WolfMerge pull request #740 from daveshah1/improve_dress tree | commitdiff
2019-02-21 Clifford WolfMerge pull request #818 from YosysHQ/clifford/dffsrfix tree | commitdiff
2019-02-21 Clifford WolfMerge pull request #786 from YosysHQ/pmgen tree | commitdiff
2019-02-21 Clifford WolfBugfix in ice40_dsp tree | commitdiff
2019-02-20 Clifford WolfAdd ice40 test_dsp_map test case generator tree | commitdiff
2019-02-20 Clifford WolfAdd "synth_ice40 -dsp" tree | commitdiff
2019-02-20 Clifford WolfImprove iCE40 SB_MAC16 model tree | commitdiff
2019-02-19 David Shahecp5: Add DDRDLLA tree | commitdiff
2019-02-19 David Shahecp5: Add DELAYF/DELAYG blackboxes tree | commitdiff
2019-02-19 Clifford WolfAdd first draft of functional SB_MAC16 model tree | commitdiff
2019-02-18 Eddie HungMerge branch 'dff_init' into read_aiger tree | commitdiff
2019-02-17 Eddie HungRevert "Add INIT parameter to all ff/latch cells" tree | commitdiff
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