added $pmux cell translation
[yosys.git] / techlibs /
2014-02-07 Clifford WolfAdded $slice and $concat cell types
2014-02-03 Clifford WolfAdded TRANSPARENT parameter to $memrd (and RD_TRANSPARE...
2014-01-31 Clifford WolfMore changes to techlibs/common/simlib.v for LEC
2014-01-29 Clifford WolfAdded test comments to techlibs/cmos/cmos_cells.lib
2014-01-28 Clifford WolfMajor rewrite of techlibs/common/simlib.v for LEC ...
2014-01-20 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-19 Clifford WolfAdded $assert cell
2014-01-18 Clifford WolfFixed $lut simlib model for a wider range of tools
2014-01-18 Clifford WolfMore changes to simlib to make it friendlier to a wider...
2014-01-18 Clifford WolfFixed a type in $mem model in simlib.v
2014-01-18 Ahmed IrfanMerge branch 'master' of https://github.com/ahmedirfan1...
2014-01-18 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-18 Ahmed Irfanpmux2mux
2014-01-18 Clifford WolfRemoved cases of trailing comma in stdcells.v
2014-01-18 Clifford WolfAdded $bu0 cell to simlib.v
2014-01-17 Clifford WolfAdded techlibs/common/pmux2mux.v
2014-01-17 Ahmed IrfanMerge branch 'master' of https://github.com/ahmedirfan1...
2014-01-17 Ahmed IrfanMerge branch 'master' of https://github.com/ahmedirfan1...
2014-01-15 Ahmed IrfanMerge branch 'master' of https://github.com/ahmedirfan1...
2014-01-14 Ahmed IrfanMerge branch 'master' of https://github.com/ahmedirfan1...
2014-01-03 Ahmed Irfansplitnet -driver feature
2014-01-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-03 Ahmed Irfanbtor
2013-12-31 Clifford WolfVarious small cleanups in stdcells.v techmap code
2013-12-28 Clifford WolfAdded $bu0 cell (for easy correct $eq/$ne mapping)
2013-12-27 Clifford WolfAdded support for non-const === and !== (for miter...
2013-11-24 Clifford WolfUsing simplemap mappers from techmap
2013-11-24 Clifford WolfRenamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 Clifford WolfAdded "techmap -share_map" option
2013-11-24 Clifford WolfFixed xilinx/example_sim_counter test bench
2013-11-23 Clifford WolfAdded more generic _TECHMAP_ wire mechanism to techmap...
2013-11-21 Clifford WolfUpdated abc
2013-11-19 Clifford WolfInstall simlib in datdir
2013-11-18 Clifford WolfAdded commented-out osu025 maping commands to cmos...
2013-11-10 Clifford WolfCleanups and bugfixes in response to new internal cell...
2013-11-06 Clifford WolfFixed techmap of $reduce_xnor with multi-bit outputs
2013-11-06 Clifford WolfFixed techmap of $gt and $ge with multi-bit outputs
2013-11-06 Clifford WolfImproved width extension with regard to undef propagation
2013-11-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-10-31 Clifford WolfAdded DFFSR cell to techlibs/cmos/cmos_cells.lib
2013-10-27 Clifford WolfMerge pull request #12 from jameswalmsley/master
2013-10-27 James Walmsley[EXAMPLES] Ported the mojo counter example to Zynq...
2013-10-27 Clifford WolfCleanups in xilinx examples
2013-10-27 Clifford WolfAdded synth_xilinx command
2013-10-27 Clifford WolfMoved simple xilinx counter sim example to subdir
2013-10-27 Clifford WolfXilinx mojo_counter example is now working
2013-10-26 Clifford WolfRenamed techlibs/xilinx7 to techlibs/xilinx
2013-10-26 Clifford WolfImproved xilinx mojo_counter example
2013-10-26 Clifford WolfAdded another xilinx example (not funcional yet)
2013-10-18 Clifford WolfBugfix in dffsr techmap rules
2013-10-18 Clifford WolfAdded techmap rules for $sr, $dffsr and $dlatch
2013-10-18 Clifford WolfAdded $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_...
2013-10-18 Clifford WolfAdded $sr, $dffsr and $dlatch cell types
2013-10-16 Clifford WolfAdded map, par and bitgen to xlinx7 example
2013-09-15 Clifford WolfMoved common techlib files to techlibs/common
2013-09-14 Clifford WolfAdded spice testbench to techlibs/cmos
2013-09-14 Clifford WolfAdded spice backend
2013-09-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-08-27 Clifford WolfAdded mapping to techlibs/xilinx7 testbench (exposes...
2013-08-22 Clifford WolfAdded simple xilinx7 technology mapping files
2013-08-15 Clifford WolfImplemented same div-by-zero behavior as found in other...
2013-08-09 Clifford WolfAdded $div and $mod technology mapping
2013-07-23 Clifford WolfAdded $lut cells and abc lut mapping support
2013-07-09 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-07-09 Clifford WolfFixed shift ops with large right hand side
2013-06-13 Clifford WolfMore fixes for bugs found using xsthammer
2013-06-10 Clifford WolfMore sign-extension related fixes
2013-06-03 Clifford WolfImplemented technology mapping for multipliers (using...
2013-05-16 Clifford WolfMerge branch 'bugfix'
2013-04-07 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-04-07 Clifford WolfFixed clock related parameter names for $memrd and...
2013-03-28 Clifford WolfAdded EXTRA_TARGETS Makefile variable
2013-03-26 Clifford WolfTiny bugfix in simlib.v
2013-03-24 Clifford WolfFixed stdcells.v for $adff with undef reset value
2013-03-14 Clifford WolfMore support code for $sr cells
2013-01-05 Clifford Wolfadded .gitignore files
2013-01-05 Clifford Wolfinitial import