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Fixed some typos
[yosys.git]
/
techlibs
/
2016-04-02
Clifford Wolf
Merge pull request #144 from azonenberg/master
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2016-04-02
Andrew Zonenberg
Removed more debug prints
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2016-04-02
Andrew Zonenberg
Removed forgotten debug code
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2016-04-02
Andrew Zonenberg
Added GreenPak inverter support
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2016-04-02
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-04-02
Andrew Zonenberg
Added support for inferring counters with asynchronous...
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2016-04-01
Clifford Wolf
Merge pull request #143 from azonenberg/master
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commitdiff
2016-04-01
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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commitdiff
2016-04-01
Andrew Zonenberg
DFFINIT is now correctly called for all kinds of flipfl...
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2016-04-01
Andrew Zonenberg
Fixed incorrect port name in cells_map.v
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commitdiff
2016-03-31
Clifford Wolf
Added ScriptPass helper class for script-like passes
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commitdiff
2016-03-31
Andrew Zonenberg
Fixed typo (wasn't written in 2012)
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commitdiff
2016-03-31
Clifford Wolf
Renamed opt_share to opt_merge
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2016-03-31
Clifford Wolf
Renamed opt_const to opt_expr
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2016-03-31
Clifford Wolf
Fixed typo in greenpak4_counters.cc
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commitdiff
2016-03-31
Clifford Wolf
Merge pull request #142 from azonenberg/master
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2016-03-31
Andrew Zonenberg
Renamed counters pass to greenpak4_counters
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2016-03-31
Andrew Zonenberg
Added initial implementation of "counters" pass to...
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commitdiff
2016-03-31
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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commitdiff
2016-03-31
Andrew Zonenberg
Updated tech lib for greenpak4 counter with some clarif...
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commitdiff
2016-03-30
Andrew Zonenberg
Initial work on greenpak4 counter extraction. Doesn...
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commitdiff
2016-03-30
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2016-03-30
Andrew Zonenberg
Added splitnets to synth_greenpak4
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2016-03-29
Clifford Wolf
Added more cell help messages
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commitdiff
2016-03-29
Clifford Wolf
Fixed indenting in techlibs/greenpak4/gp_dff.lib
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commitdiff
2016-03-29
Clifford Wolf
Merge pull request #141 from azonenberg/master
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2016-03-29
Andrew Zonenberg
Added keep constraint to GP_SYSRESET cell
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2016-03-29
Andrew Zonenberg
Added GP_SYSRESET block
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commitdiff
2016-03-28
Clifford Wolf
Merge pull request #137 from ravenexp/master
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commitdiff
2016-03-28
Clifford Wolf
Merge pull request #138 from SebKuzminsky/help-typo
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commitdiff
2016-03-28
Clifford Wolf
Merge pull request #139 from azonenberg/master
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commitdiff
2016-03-27
Andrew Zonenberg
Added GP_COUNT8/GP_COUNT14 cells
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commitdiff
2016-03-26
Andrew Zonenberg
Changed GP_LFOSC parameter configuration
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2016-03-26
Andrew Zonenberg
Added GP_LFOSC cell
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2016-03-26
Andrew Zonenberg
Renamed GP4_V* cells to GP_V* for consistency
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2016-03-23
Clifford Wolf
Added GP_DFFS, GP_DFFR, and GP_DFFSR
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2016-03-23
Clifford Wolf
Added GP_DFF INIT parameter
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commitdiff
2016-03-21
Clifford Wolf
Improvements in synth_greenpak4, added -part option
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commitdiff
2016-03-19
Clifford Wolf
Added black box modules for all the 7-series design...
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2016-02-13
Clifford Wolf
Run dffsr2dff in synth_xilinx
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commitdiff
2016-02-07
Clifford Wolf
Work around DDR dout sim glitches in ice40 SB_IO sim...
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commitdiff
2016-02-02
Clifford Wolf
Added dffsr2dff
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commitdiff
2016-02-01
Clifford Wolf
Progress in cell library documentation
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commitdiff
2016-02-01
Clifford Wolf
Added "abc -luts" option, Improved Xilinx logic mapping
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commitdiff
2015-12-22
Clifford Wolf
Re-run ice40_opt in "synth_ice40 -abc2"
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commitdiff
2015-12-22
Clifford Wolf
Improvements in ice40_opt
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2015-12-22
Clifford Wolf
Bugfix in ice40_ffinit
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2015-12-22
Clifford Wolf
Improved ice40_ffinit
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2015-12-22
Clifford Wolf
Run opt_const before check in default scripts
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2015-12-08
Clifford Wolf
Added "synth_ice40 -abc2"
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2015-12-07
Clifford Wolf
Merge pull request #108 from cseed/master
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2015-12-06
Cotton Seed
Added LO to ICESTORM_LC for LUT cascade route.
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2015-11-26
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2015-11-26
Clifford Wolf
Added ice40_ffinit pass
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2015-11-24
Clifford Wolf
Fixed WE/RE usage in iCE40 BRAM mapping
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commitdiff
2015-11-06
Clifford Wolf
Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handling
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commitdiff
2015-10-30
Clifford Wolf
Bugfix in Xilinx LUT mapping
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commitdiff
2015-10-20
Clifford Wolf
Progress on cell help messages
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2015-10-17
Clifford Wolf
Progress on cell help messages
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2015-10-14
Clifford Wolf
Added "prep" command
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2015-10-14
Clifford Wolf
Added more cell descriptions
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2015-10-14
Clifford Wolf
Added first help messages for cell types
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2015-10-13
Clifford Wolf
Added examples/ top-level directory
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2015-09-25
Clifford Wolf
Added read-enable to memory model
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2015-09-18
Clifford Wolf
Added nlutmap
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2015-09-18
Clifford Wolf
Renamed GreenPAK4 cells, improved GP4 DFF mapping
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commitdiff
2015-09-16
Clifford Wolf
Fixed copy&paste typo in synth_greenpak4
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commitdiff
2015-09-16
Clifford Wolf
Added GreenPAK4 skeleton
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2015-09-10
Clifford Wolf
Fixed ice40 handling of negclk RAM40
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2015-08-22
Clifford Wolf
Switched to Python 3
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2015-08-16
Clifford Wolf
Another bugfix for ice40 and xilinx brams_init make...
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commitdiff
2015-08-16
Clifford Wolf
Fixed Makefile rules for generated share files
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2015-08-16
Clifford Wolf
Added $tribuf and $_TBUF_ sim models
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2015-08-16
Clifford Wolf
Added tribuf command
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2015-08-16
Clifford Wolf
Added $tribuf and $_TBUF_ cell types
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2015-08-14
Larry Doolittle
Another block of spelling fixes
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2015-08-13
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2015-08-12
Clifford Wolf
Adjust makefiles to work with out-of-tree builds
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2015-08-12
Clifford Wolf
Improved handling of "keep" attributes in hierarchical...
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2015-08-06
Clifford Wolf
Merge pull request #69 from zeldin/master
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2015-08-06
Marcus Comstedt
Added iCE40 WARMBOOT cell
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commitdiff
2015-07-31
Clifford Wolf
Added WORDS parameter to $meminit
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2015-07-27
Clifford Wolf
Don't write a 17th memory bit in ice40/cells_sim (by...
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2015-07-20
Clifford Wolf
iCE40 DFF sim models: init Q regs to 0
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2015-07-18
Clifford Wolf
Avoid tristate warning for blackbox ice40/cells_sim.v
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2015-07-06
Clifford Wolf
Improved liberty file test case
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2015-07-02
Clifford Wolf
Added "synth -nofsm"
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2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2015-06-20
Clifford Wolf
iCE40: set min bram efficiency to 2%
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2015-06-15
Clifford Wolf
Added "synth -nordff -noalumacc"
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2015-06-09
Clifford Wolf
synth_ice40 now flattens by default
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2015-05-31
Clifford Wolf
Added iCE40 PLL cells
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2015-05-26
Clifford Wolf
Added output args to synth_ice40
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2015-05-23
Clifford Wolf
improved ice40 SB_IO sim model
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2015-05-23
Clifford Wolf
Added ice40 SB_IO sim model
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2015-05-17
Clifford Wolf
Verific build fixes
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2015-04-27
Clifford Wolf
ice40_opt bugfix
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2015-04-27
Clifford Wolf
iCE40: SB_CARRY const fold -> unmap SB_LUT
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2015-04-27
Clifford Wolf
Added simplemap $lut support
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2015-04-27
Clifford Wolf
Added iCE40 const folding support for SB_CARRY
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