Merge remote-tracking branch 'origin/pmux2shiftx' into xc7mux
[yosys.git] / techlibs /
2019-04-11 Eddie HungMerge remote-tracking branch 'origin/pmux2shiftx' into...
2019-04-11 Eddie HungMerge remote-tracking branch 'origin/pmux2shiftx' into...
2019-04-11 Eddie HungFix cells_map.v some more
2019-04-11 Eddie HungMore fine tuning
2019-04-11 Eddie HungFix cells_map.v
2019-04-11 Eddie HungFix typo
2019-04-11 Eddie HungJuggle opt calls in synth_xilinx
2019-04-11 Eddie HungMerge branch 'xaig' into xc7mux
2019-04-11 Eddie HungWIP for cells_map.v -- maybe working?
2019-04-10 Eddie HungTry splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1
2019-04-10 Eddie HungFix for when B_SIGNED = 1
2019-04-10 Eddie HungUpdate doc for synth_xilinx
2019-04-10 Eddie HungMerge branch 'xaig' into xc7mux
2019-04-10 Eddie Hungff_map.v after abc
2019-04-10 Eddie HungTidy up
2019-04-10 Eddie HungMove map_cells to before map_luts
2019-04-10 Eddie HungWIP for $shiftx to wide mux
2019-04-10 Eddie HungUpdate LUT delays
2019-04-09 Eddie HungAdd cells.lut to techlibs/xilinx/
2019-04-09 Eddie Hungsynth_xilinx to call abc with -lut +/xilinx/cells.lut
2019-04-09 Eddie HungAdd delays to cells.box
2019-04-09 Eddie Hungsynth_xilinx with abc9 to use -box
2019-04-09 Eddie HungAdd techlibs/xilinx/cells.box
2019-04-09 Eddie HungAdd support for synth_xilinx -abc9 and ignore abc9...
2019-04-08 Eddie HungMerge branch 'master' into xaig
2019-03-22 Clifford WolfMerge pull request #889 from YosysHQ/clifford/fix888
2019-03-22 Clifford WolfMerge pull request #890 from YosysHQ/clifford/fix887
2019-03-22 David ShahMerge pull request #891 from YosysHQ/xilinx_keep
2019-03-22 David Shahxilinx: Add keep attribute where appropriate
2019-03-19 Clifford WolfMerge pull request #885 from YosysHQ/clifford/fix873
2019-03-19 Clifford WolfAdd Xilinx negedge FFs to synth_xilinx dffinit call...
2019-03-19 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-03-14 Clifford WolfMerge pull request #869 from cr1901/win-shell
2019-03-13 Clifford WolfMerge pull request #868 from YosysHQ/clifford/fixmem
2019-03-12 Clifford WolfRemove ice40/cells_sim.v hack to avoid warning for...
2019-03-09 Clifford WolfFix typo in ice40_braminit help msg
2019-03-09 Clifford WolfMerge pull request #859 from smunaut/ice40_braminit
2019-03-07 Sylvain Munautice40: Run ice40_braminit pass by default
2019-03-07 Sylvain Munautice40: Add ice40_braminit pass to allow initialization...
2019-03-07 Clifford WolfMerge pull request #856 from kprasadvnsi/master
2019-03-07 Clifford WolfAdd link to SF2 / igloo2 macro library guide
2019-03-07 Clifford WolfImprovements in sf2 cells_sim.v
2019-03-06 Clifford WolfAdd sf2 techmap rules for more FF types
2019-03-06 Clifford WolfRefactor SF2 iobuf insertion, Add clkint insertion
2019-03-06 Clifford WolfImprovements in SF2 flow and demo
2019-03-05 Clifford WolfMerge pull request #842 from litghost/merge_upstream
2019-03-05 Clifford WolfMerge pull request #850 from daveshah1/ecp5_warn_conflict
2019-03-05 Clifford WolfMerge pull request #851 from kprasadvnsi/master
2019-03-05 Clifford WolfMerge pull request #852 from ucb-bar/firrtlfixes
2019-03-05 Clifford WolfUse "write_edif -pvector bra" for Xilinx EDIF files
2019-03-04 Keith RothmanRevert BRAM WRITE_MODE changes.
2019-03-04 David Shahecp5: Demote conflicting FF init values to a warning
2019-03-01 Keith RothmanRevert FF models to include IS_x_INVERTED parameters.
2019-03-01 Keith RothmanUse singular for disabling of DRAM or BRAM inference.
2019-03-01 Keith RothmanModify arguments to match existing style.
2019-03-01 Keith RothmanChanges required for VPR place and route synth_xilinx.
2019-03-01 Clifford WolfMerge pull request #841 from mmicko/master
2019-03-01 Miodrag MilanovicFix ECP5 cells_sim for iverilog
2019-03-01 Clifford WolfMerge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
2019-03-01 Elmsice40: use 2 bits for READ/WRITE MODE for SB_RAM map
2019-02-28 Larry DoolittleReduce amount of trailing whitespace in code base
2019-02-28 Clifford WolfMerge pull request #794 from daveshah1/ecp5improve
2019-02-28 Clifford WolfMerge pull request #827 from ucb-bar/firrtlfixes
2019-02-26 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-02-26 Larry Doolittletechlibs/greenpak4/cells_map.v: Harmonize whitespace...
2019-02-26 Larry DoolittleClean up some whitepsace outliers
2019-02-25 David Shahecp5: Compatibility with Migen AsyncResetSynchronizer
2019-02-24 Clifford WolfMerge pull request #812 from ucb-bar/arrayhierarchyfixes
2019-02-24 Clifford WolfMerge pull request #824 from litghost/fix_reduce_on_ff
2019-02-22 Clifford WolfMerge pull request #819 from YosysHQ/clifford/optd
2019-02-22 Clifford WolfMerge pull request #820 from YosysHQ/clifford/fix810
2019-02-22 Clifford WolfMerge pull request #740 from daveshah1/improve_dress
2019-02-21 Eddie HungMerge branch 'read_aiger' into xaig
2019-02-21 Eddie HungMerge branch 'read_aiger' into xaig
2019-02-21 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-02-21 Clifford WolfMerge pull request #818 from YosysHQ/clifford/dffsrfix
2019-02-21 Clifford WolfMerge pull request #786 from YosysHQ/pmgen
2019-02-21 Eddie HungMerge branch 'clifford/dffsrfix' of https://github...
2019-02-21 Clifford WolfBugfix in ice40_dsp
2019-02-20 Eddie Hungsynth to take -abc9 argument
2019-02-20 Clifford WolfAdd ice40 test_dsp_map test case generator
2019-02-20 Clifford WolfAdd "synth_ice40 -dsp"
2019-02-20 Clifford WolfImprove iCE40 SB_MAC16 model
2019-02-19 Eddie HungMerge branch 'master' into xaig
2019-02-19 Eddie HungMerge branch 'master' into read_aiger
2019-02-19 David Shahecp5: Add DDRDLLA
2019-02-19 David Shahecp5: Add DELAYF/DELAYG blackboxes
2019-02-19 Clifford WolfAdd first draft of functional SB_MAC16 model
2019-02-18 Eddie HungMerge branch 'dff_init' into read_aiger
2019-02-17 Eddie HungRevert "Add INIT parameter to all ff/latch cells"
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into dff_init
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-02-17 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-02-14 Eddie Hungsynth_ice40 to have new -abc9 arg
2019-02-13 Eddie HungMerge remote-tracking branch 'origin/read_aiger' into...
2019-02-13 Eddie HungMerge https://github.com/YosysHQ/yosys into xaig
2019-02-13 David Shahecp5: Add ECLKSYNCB blackbox
2019-02-12 David Shahecp5: Full set of IO-related blackboxes
2019-02-08 Eddie HungMerge remote-tracking branch 'origin/dff_init' into...
2019-02-06 Eddie HungCope WIDTH of ff/latch cells is default of zero
next