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Merge branch 'master' of github.com:YosysHQ/yosys
[yosys.git] / techlibs /
2020-01-07 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys tree | commitdiff
2020-01-07 Eddie HungMerge pull request #1181 from YosysHQ/xaig_dff tree | commitdiff
2020-01-07 Eddie HungFix DSP48E1 sim tree | commitdiff
2020-01-06 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff tree | commitdiff
2020-01-06 Eddie HungMerge pull request #1617 from YosysHQ/eddie/abc9_dsp_re... tree | commitdiff
2020-01-06 Eddie HungWrap arrival functions inside `YOSYS too tree | commitdiff
2020-01-06 Eddie HungFix return value of arrival time functions, fix word tree | commitdiff
2020-01-06 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff tree | commitdiff
2020-01-06 Eddie HungMerge pull request #1582 from nakengelhardt/abc_scratch... tree | commitdiff
2020-01-06 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff tree | commitdiff
2020-01-05 Miodrag MilanovićMerge pull request #1611 from YosysHQ/mmicko/wrapcarry_fix tree | commitdiff
2020-01-04 Miodrag MilanovicValid to have attribute starting with SB_CARRY. tree | commitdiff
2020-01-03 N. EngelhardtMerge branch 'master' of https://github.com/YosysHQ... tree | commitdiff
2020-01-03 Eddie HungFix spacing tree | commitdiff
2020-01-02 Eddie HungDrive $[ABCD] explicitly tree | commitdiff
2020-01-02 whitequarkMerge pull request #1604 from whitequark/unify-ram... tree | commitdiff
2020-01-02 Eddie Hungsynth_xilinx -dff to work with abc too tree | commitdiff
2020-01-02 Eddie HungMerge remote-tracking branch 'origin/master' into eddie... tree | commitdiff
2020-01-02 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff tree | commitdiff
2020-01-02 Eddie HungUpdate comments tree | commitdiff
2020-01-02 Eddie Hungabc9 -keepff -> -dff; refactor dff operations tree | commitdiff
2020-01-02 Clifford WolfMerge pull request #1609 from YosysHQ/clifford/fix1596 tree | commitdiff
2020-01-02 Eddie HungMerge pull request #1601 from YosysHQ/eddie/synth_retime tree | commitdiff
2020-01-02 Eddie HungMerge pull request #1608 from YosysHQ/eddie/ifndef_YOSYS tree | commitdiff
2020-01-02 Eddie Hungifndef __ICARUS__ -> ifdef YOSYS tree | commitdiff
2020-01-02 Eddie Hungifdef __ICARUS__ -> ifndef YOSYS tree | commitdiff
2020-01-02 Eddie HungRework abc9's DSP48E1 model tree | commitdiff
2020-01-01 Eddie HungMerge pull request #1606 from YosysHQ/eddie/improve_tests tree | commitdiff
2020-01-01 Eddie HungFix anlogic async flop mapping tree | commitdiff
2020-01-01 Eddie HungClamp -46ps for FDPE* too tree | commitdiff
2020-01-01 Eddie HungRestore abc9 -keepff tree | commitdiff
2020-01-01 whitequarkHarmonize BRAM/LUTRAM descriptions across all of Yosys. tree | commitdiff
2020-01-01 Eddie HungRe-arrange FD order tree | commitdiff
2020-01-01 Eddie HungMissing character tree | commitdiff
2020-01-01 Eddie HungCleanup xilinx boxes tree | commitdiff
2020-01-01 Eddie HungCleanup ice40 boxes tree | commitdiff
2020-01-01 Eddie HungCleanup ecp5 boxes tree | commitdiff
2019-12-31 Eddie HungUpdate abc9_xc7.box comments tree | commitdiff
2019-12-31 Eddie HungFDCE ports to be alphabetical tree | commitdiff
2019-12-31 Eddie HungFix attributes on $__ABC9_ASYNC[01] whitebox tree | commitdiff
2019-12-31 Eddie HungFix incorrect $__ABC9_ASYNC[01] box tree | commitdiff
2019-12-30 Eddie HungUpdate timings for Xilinx S7 cells tree | commitdiff
2019-12-30 Eddie HungDo not offset FD* box timings due to -46ps Tsu tree | commitdiff
2019-12-30 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff tree | commitdiff
2019-12-30 Eddie HungTidy up abc9_map.v tree | commitdiff
2019-12-30 Eddie HungAdd "synth_xilinx -dff" option, cleanup abc9 tree | commitdiff
2019-12-30 Eddie HungUpdate doc that "-retime" calls abc with "-dff -D 1" tree | commitdiff
2019-12-30 Eddie HungDisable synth_gowin -abc9 as it offers no advantages yet tree | commitdiff
2019-12-30 Eddie HungRevert "Revert "synth_* with -retime option now calls... tree | commitdiff
2019-12-30 Miodrag MilanovićMerge pull request #1589 from YosysHQ/iopad_default tree | commitdiff
2019-12-30 Eddie HungMerge pull request #1599 from YosysHQ/eddie/retry_1588 tree | commitdiff
2019-12-30 Eddie HungMerge pull request #1600 from YosysHQ/eddie/cleanup_ecp5 tree | commitdiff
2019-12-28 Miodrag MilanovicMerge remote-tracking branch 'origin/master' into iopad... tree | commitdiff
2019-12-28 Eddie HungNitpick cleanup for ecp5 tree | commitdiff
2019-12-25 Marcin KościelnickiMerge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen tree | commitdiff
2019-12-23 Marcin Kościelnickixilinx: Test our DSP48A/DSP48A1 simulation models. tree | commitdiff
2019-12-22 Marcin Kościelnickixilinx_dsp: Initial DSP48A/DSP48A1 support. tree | commitdiff
2019-12-21 Miodrag MilanovicAddressed review comments tree | commitdiff
2019-12-21 Miodrag Milanoviciopad no op for compatibility with old scripts tree | commitdiff
2019-12-21 Miodrag MilanovicMake iopad option default for all xilinx flows tree | commitdiff
2019-12-20 Eddie HungMerge pull request #1588 from YosysHQ/eddie/xaiger_cleanup tree | commitdiff
2019-12-20 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff tree | commitdiff
2019-12-20 Eddie HungAdd abc9_arrival times for RAM{32,64}M tree | commitdiff
2019-12-20 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff tree | commitdiff
2019-12-20 Eddie HungAdd RAM{32,64}M to abc9_map.v tree | commitdiff
2019-12-20 Eddie HungMerge pull request #1585 from YosysHQ/eddie/fix_abc9_lut tree | commitdiff
2019-12-20 Eddie HungMerge pull request #1587 from YosysHQ/revert-1558-eddie... tree | commitdiff
2019-12-20 Eddie HungRevert "Optimise write_xaiger" tree | commitdiff
2019-12-19 Eddie HungAdd RAM{32,64}M to abc9_map.v tree | commitdiff
2019-12-19 Eddie HungSplit into $__ABC9_ASYNC[01], do not add cell->type... tree | commitdiff
2019-12-19 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff tree | commitdiff
2019-12-19 Eddie HungMerge pull request #1581 from YosysHQ/clifford/fix1565 tree | commitdiff
2019-12-19 Eddie HungMerge pull request #1558 from YosysHQ/eddie/xaiger_cleanup tree | commitdiff
2019-12-19 Eddie HungMerge pull request #1569 from YosysHQ/eddie/fix_1531 tree | commitdiff
2019-12-19 Eddie HungMerge pull request #1571 from YosysHQ/eddie/fix_1570 tree | commitdiff
2019-12-19 Marcin Kościelnickixilinx: Add simulation models for remaining CLB primitives. tree | commitdiff
2019-12-19 Marcin Kościelnickixilinx_dffopt: Keep order of LUT inputs. tree | commitdiff
2019-12-18 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys tree | commitdiff
2019-12-18 David ShahMerge pull request #1563 from YosysHQ/dave/async-prld tree | commitdiff
2019-12-18 Eddie HungMerge pull request #1572 from nakengelhardt/scratchpad_pass tree | commitdiff
2019-12-18 Marcin Kościelnickixilinx: Add xilinx_dffopt pass (#1557) tree | commitdiff
2019-12-18 Marcin Kościelnickixilinx: Improve flip-flop handling. tree | commitdiff
2019-12-17 Eddie HungMerge pull request #1574 from YosysHQ/eddie/xilinx_lutram tree | commitdiff
2019-12-17 Eddie HungMerge pull request #1521 from dh73/diego/memattr tree | commitdiff
2019-12-16 Eddie HungAdd unconditional match blocks for force RAM tree | commitdiff
2019-12-16 Eddie HungUpdate xc7/xcu bram rules tree | commitdiff
2019-12-16 Eddie HungMerge branch 'diego/memattr' of https://github.com... tree | commitdiff
2019-12-16 Eddie HungMerge branch 'eddie/xilinx_lutram' of github.com:YosysH... tree | commitdiff
2019-12-16 Eddie HungPopulate DID/DOD even if unused tree | commitdiff
2019-12-16 Eddie HungRename *RAM{32,64}M rules to RAM{32X2,64X1}Q tree | commitdiff
2019-12-16 Diego HRemoving fixed attribute value to !ramstyle rules tree | commitdiff
2019-12-16 Diego HMerging attribute rules into a single match block;... tree | commitdiff
2019-12-16 Eddie HungMerge pull request #1575 from rodrigomelo9/master tree | commitdiff
2019-12-16 Eddie HungMerge pull request #1577 from gromero/for-yosys tree | commitdiff
2019-12-13 Diego HRefactoring memory attribute matching based on IEEE... tree | commitdiff
2019-12-13 Eddie HungMerge pull request #1533 from dh73/bram_xilinx tree | commitdiff
2019-12-13 Eddie HungDisable RAM16X1D match rule; carry-over from LUT4 arches tree | commitdiff
2019-12-13 Eddie HungRAM64M8 to also have [5:0] for address tree | commitdiff
2019-12-13 Eddie HungAdd RAM32X6SDP and RAM64X3SDP modes tree | commitdiff
2019-12-13 Eddie HungFix RAM64M model to have 6 bit address bus tree | commitdiff
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