Merge pull request #1751 from boqwxp/add_assert
[yosys.git] / techlibs /
2020-03-11 Eddie HungMerge pull request #1743 from YosysHQ/eddie/abc9_keep
2020-03-11 Eddie HungMerge pull request #1744 from YosysHQ/eddie/fix1675
2020-03-10 David ShahMerge pull request #1721 from YosysHQ/dave/tribuf-unused
2020-03-09 Eddie HungMerge pull request #1747 from YosysHQ/claire/partselfix
2020-03-09 N. EngelhardtMerge pull request #1716 from zeldin/ecp5_fix
2020-03-06 N. Engelhardtremove unused parameters
2020-03-05 Eddie HungMerge pull request #1739 from YosysHQ/eddie/issue1738
2020-03-05 Eddie Hungice40: fix specify for ICE40_{LP,U}
2020-03-04 Eddie Hungice40: fix implicit signal in specify, also clamp negat...
2020-03-04 Eddie HungMerge pull request #1735 from YosysHQ/eddie/abc9_dsp48e1
2020-03-04 Eddie Hungxilinx: consider DSP48E1.ADREG
2020-03-04 Eddie Hungxilinx: cleanup DSP48E1 handling for abc9
2020-03-04 Eddie Hungxilinx: improve specify for DSP48E1
2020-03-04 Eddie Hungxilinx: missing DSP48E1.PCIN timing from abc9_{map...
2020-03-03 N. EngelhardtMerge pull request #1691 from ZirconiumX/use-flowmap...
2020-03-03 Claire WolfMerge pull request #1718 from boqwxp/precise_locations
2020-03-03 Claire WolfMerge pull request #1681 from YosysHQ/eddie/fix1663
2020-03-03 Claire WolfMerge pull request #1519 from YosysHQ/eddie/submod_po
2020-03-02 Eddie HungMerge pull request #1724 from YosysHQ/eddie/abc9_specify
2020-03-02 N. EngelhardtMerge pull request #1729 from rqou/coolrunner2
2020-03-02 R. Oucoolrunner2: Attempt to give wires/cells more meaningfu...
2020-03-02 R. Oucoolrunner2: Fix invalid multiple fanouts of XOR/OR...
2020-03-02 R. Oucoolrunner2: Fix packed register+input buffer insertion
2020-03-02 R. Oucoolrunner2: Insert many more required feedthrough...
2020-02-28 Dan RavensloftAdd -flowmap to synth and synth_ice40
2020-02-27 Eddie HungRemove RAMB{18,36}E1 from cells_xtra.py
2020-02-27 Eddie Hungxilinx: Update RAMB* specify entries
2020-02-27 Eddie Hungice40: add delays to SB_CARRY
2020-02-27 Eddie Hungxilinx: add delays to INV
2020-02-27 Eddie HungMore +/ice40/cells_sim.v fixes
2020-02-27 Eddie HungMake +/xilinx/cells_sim.v legal
2020-02-27 Eddie HungGet rid of (* abc9_{arrival,required} *) entirely
2020-02-27 Eddie Hungabc9_ops: use TimingInfo for -prep_{lut,box} too
2020-02-27 Eddie HungExpand +/xilinx/cells_sim.v to keep ICARUS and non...
2020-02-27 Eddie Hungice40: fix specify for inverted clocks
2020-02-27 Eddie HungFix tests by gating some specify constructs from iverilog
2020-02-27 Eddie Hungabc9_ops: ignore (* abc9_flop *) if not '-dff'
2020-02-27 Eddie Hungice40: specify fixes
2020-02-27 Eddie Hungice40: move over to specify blocks for -abc9
2020-02-27 Eddie Hungsynth_ecp5: use +/abc9_model.v
2020-02-27 Eddie HungUpdate xilinx for ABC9
2020-02-27 Eddie HungCreate +/abc9_model.v for $__ABC9_{DELAY,FF_}
2020-02-27 Eddie Hungecp5: remove small LUT entries
2020-02-27 Eddie HungFix commented out specify statement
2020-02-27 Eddie Hungxilinx: improve specify functionality
2020-02-27 Eddie Hungecp5: deprecate abc9_{arrival,required} and *.{lut...
2020-02-27 Eddie Hungxilinx: use specify blocks in place of abc9_{arrival...
2020-02-27 Eddie HungAuto-generate .box/.lut files from specify blocks
2020-02-27 Eddie Hungabc9_ops: -prep_box, to be called once
2020-02-27 Eddie Hungabc9_ops: -prep_lut and -write_lut to auto-generate...
2020-02-27 Claire WolfMerge pull request #1709 from rqou/coolrunner2_counter
2020-02-27 Claire WolfMerge pull request #1708 from rqou/coolrunner2-buf-fix
2020-02-27 Piotr Binkowskixilinx: mark IOBUFDSE3 IOB pin as external
2020-02-26 Miodrag MilanovićMerge pull request #1705 from YosysHQ/logger_pass
2020-02-22 Marcus Comstedtecp5: Add missing parameter to \$__ECP5_PDPW16KD
2020-02-21 Eddie HungMerge pull request #1703 from YosysHQ/eddie/specify_improve
2020-02-20 Claire WolfMerge pull request #1642 from jjj11x/jjj11x/sv-enum
2020-02-17 R. Oucoolrunner2: Use extract_counter to optimize counters
2020-02-17 R. Oucoolrunner2: Separate and improve buffer cell insertion...
2020-02-15 Miodrag MilanovićMerge pull request #1706 from YosysHQ/mmicko/remove_exe...
2020-02-15 Miodrag MilanovicRemove executable flag from files
2020-02-14 Miodrag MilanovićMerge pull request #1701 from nakengelhardt/rpc-test
2020-02-14 Eddie HungMerge pull request #1700 from YosysHQ/eddie/abc9_fixes
2020-02-13 Eddie Hungabc9: deprecate abc9_ff.init wire for (* abc9_init...
2020-02-13 Claire WolfMerge pull request #1694 from rqou/json_compat_fix
2020-02-13 N. EngelhardtMerge pull request #1679 from thasti/delay-parsing
2020-02-10 Eddie Hungabc9: cleanup
2020-02-10 Eddie HungMerge pull request #1670 from rodrigomelo9/master
2020-02-10 N. EngelhardtMerge pull request #1669 from thasti/pyosys-attrs
2020-02-07 Eddie HungRemove unnecessary comma
2020-02-07 Eddie HungMerge pull request #1687 from YosysHQ/eddie/fix_ystests
2020-02-07 Eddie Hungtechmap: fix shiftx2mux decomposition
2020-02-07 Marcin Kościelnickixilinx: Add support for LUT RAM on LUT4-based devices.
2020-02-07 Marcin Kościelnickixilinx: Initial support for LUT4 devices.
2020-02-07 Eddie HungMerge pull request #1685 from dh73/gowin
2020-02-07 whitequarkMerge pull request #1683 from whitequark/write_verilog...
2020-02-07 Marcin Kościelnickixilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 Marcin Kościelnickixilinx: Add support for Spartan 3A DSP block RAMs.
2020-02-06 Eddie HungMerge pull request #1684 from YosysHQ/eddie/xilinx_arit...
2020-02-06 Diego HRemoving cells_sim.v from bram techmap pass
2020-02-06 Eddie HungFix $lcu -> MUXCY mapping, credit @mwkmwkmwk
2020-02-06 Eddie HungFix/cleanup +/xilinx/arith_map.v
2020-02-06 Eddie HungMerge pull request #1682 from YosysHQ/eddie/opt_after_t...
2020-02-06 Eddie Hungsynth_*: call 'opt -fast' after 'techmap'
2020-02-06 Eddie Hungshiftx2mux: fix select out of bounds
2020-02-05 Eddie HungMerge pull request #1576 from YosysHQ/eddie/opt_merge_init
2020-02-05 Eddie HungMerge pull request #1650 from YosysHQ/eddie/shiftx2mux
2020-02-05 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2020-02-05 Eddie HungMerge pull request #1638 from YosysHQ/eddie/fix1631
2020-02-05 Eddie HungMerge pull request #1661 from YosysHQ/eddie/abc9_required
2020-02-03 Rodrigo A. MeloMerge branch 'master' into master
2020-02-03 Marcelina KościelnickaAdd opt_lut_ins pass. (#1673)
2020-02-03 Rodrigo Alejandro... Merge branch 'master' of https://github.com/YosysHQ...
2020-02-02 David ShahMerge pull request #1647 from YosysHQ/dave/sprintf
2020-02-02 David ShahMerge pull request #1657 from YosysHQ/dave/xilinx-dsp...
2020-02-02 Marcin Kościelnickixilinx: use RAM32M/RAM64M for memories with two read...
2020-02-01 Eddie HungMerge branch 'master' into eddie/submod_po
2020-01-30 Claire WolfMerge pull request #1503 from YosysHQ/eddie/verific_help
2020-01-30 Claire WolfMerge pull request #1654 from YosysHQ/eddie/sby_fix69
2020-01-29 Claire WolfMerge branch 'vector_fix' of https://github.com/Kmanfi...
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