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[yosys.git] / techlibs /
2021-10-02 Marcelina KościelnickaHook up $aldff support in various passes.
2021-10-02 Marcelina KościelnickaAdd $aldff and $aldffe: flip-flops with async load.
2021-09-09 Eddie Hungabc9: replace cell type/parameters if derived type...
2021-08-29 kittennbfive[ECP5] fix wrong link for syn_* attributes description...
2021-08-22 ECP5-PCIeAdd DLLDELD
2021-08-20 Pepijn de VosGowin: deal with active-low tristate (#2971)
2021-08-17 Sylvain Munautice40: Fix typo in SB_CARRY specify for LP/UltraPlus
2021-08-11 Marcelina KościelnickaAdd v2 memory cells.
2021-07-30 Maciej DudekFixes xc7 BRAM36s
2021-07-29 Marcelina Kościelnickaopt_lut: Allow more than one -dlogic per cell type.
2021-07-28 Marcelina Kościelnickamemory: Introduce $meminit_v2 cell, with EN input.
2021-07-10 Marcelina Kościelnickaice40: Fix LUT input indices in opt_lut -dlogic (again).
2021-07-06 gatecatecp5: Add DCSC blackbox
2021-06-09 Claire XenMerge pull request #2817 from YosysHQ/claire/fixemails
2021-06-09 Claire Xenia WolfFix icestorm links
2021-06-09 Claire Xenia WolfUse HTTPS for website links, gatecat email
2021-06-09 Claire Xenia WolfFix files with CRLF line endings
2021-06-07 Claire Xenia WolfFixing old e-mail addresses and deadnames
2021-05-15 gatecatintel_alm: Fix illegal carry chains
2021-05-15 gatecatintel_alm: Add global buffer insertion
2021-05-15 gatecatintel_alm: Add IO buffer insertion
2021-05-12 Adam GreigAdd missing parameters for MULT18X18D and ALU54B to...
2021-04-27 Miodrag MilanovićMerge pull request #2738 from mdko/xilinx-blif
2021-04-27 Michael ChristensenFix use of blif name in synth_xilinx command
2021-04-21 Claire XenMerge pull request #2669 from YosysHQ/claire/ice40defaults
2021-04-20 Claire Xenia WolfAdd default assignments to other SB_* simulation models
2021-04-20 Claire Xenia WolfAdd default assignments to SB_LUT4
2021-04-17 Loftyquicklogic: ABC9 synthesis
2021-04-09 Stefan Riesenbergersf2: fix name of AND modules ls180
2021-03-30 Eddie Hungabc9: fix SCC issues (#2694)
2021-03-19 Miodrag MilanovićMerge pull request #2681 from msinger/fix-issue2606
2021-03-18 Loftyquicklogic: PolarPro 3 support
2021-03-17 gatecatBlackbox all whiteboxes after synthesis
2021-03-11 whitequarkMerge pull request #2642 from whitequark/cxxrtl-noproc...
2021-03-09 whitequarkMerge pull request #2643 from zachjs/fix-param-no-defau...
2021-03-08 Marcelina Kościelnickamemory_dff: Remove now-useless write port handling. working-ls180
2021-03-01 Claire XenMerge pull request #2523 from tomverbeure/define_synthesis
2021-03-01 Claire XenMerge pull request #2524 from bkbncn/patch-1
2021-02-25 whitequarkMerge pull request #2554 from hzeller/master
2021-02-24 Marcelina KościelnickaFix syntax error in adff2dff.v
2021-02-23 whitequarkMerge pull request #2594 from zachjs/func-arg-width
2021-02-23 William D. Jonesmachxo2: Switch to LUT4 sim model which propagates...
2021-02-23 William D. Jonesmachxo2: Add experimental status to help.
2021-02-23 William D. Jonesmachxo2: Add DCCA and DCMA blackbox primitives.
2021-02-23 William D. Jonesmachxo2: Fix reversed interpretation of REG_SD config...
2021-02-23 William D. Jonesmachxo2: Tristate is active-low.
2021-02-23 William D. Jonesmachxo2: Fix typos in FACADE_FF sim model.
2021-02-23 William D. Jonesmachxo2: Fix naming of TRELLIS_IO ports to match PIO...
2021-02-23 William D. Jonesmachxo2: Improve help_mode output in synth_machxo2.
2021-02-23 William D. Jonesmachxo2: Use attrmvcp pass to move LOC and src attribut...
2021-02-23 William D. Jonesmachxo2: Add missing OSCH oscillator primitive.
2021-02-23 William D. Jonesmachxo2: Add -noiopad option to synth_machxo2.
2021-02-23 William D. Jonesmachxo2: Use correct INITVAL for LUT1 in FACADE_SLICE.
2021-02-23 William D. Jonesmachxo2: Fix cells_sim typo where OFX1 was multiply...
2021-02-23 William D. Jonesmachxo2: synth_machxo2 now maps ports to FACADE_IO.
2021-02-23 William D. Jonesmachxo2: Add initial value for Q in FACADE_FF.
2021-02-23 William D. Jonesmachxo2: Add FACADE_IO simulation model. More comments...
2021-02-23 William D. Jonesmachxo2: Add FACADE_SLICE simulation model.
2021-02-23 William D. Jonesmachxo2: Improve FACADE_FF simulation model.
2021-02-23 William D. Jonesmachxo2: Improve LUT4 techmap. Use same output port...
2021-02-23 William D. Jonesmachxo2: Add dff.ys test, fix another cells_map.v typo.
2021-02-23 William D. Jonesmachxo2: Fix more oversights in machxo2 models. logic...
2021-02-23 William D. Jonesmachxo2: Fix typos. test/arch/run-test.sh passes.
2021-02-23 William D. Jonesmachxo2: Create basic techlibs and synth_machxo2 pass.
2021-02-15 Claire XenMerge pull request #2574 from dh73/master
2021-02-12 gatecatMerge pull request #2585 from YosysHQ/dave/nexus-dotproduct
2021-02-04 whitequarkMerge pull request #2529 from zachjs/unnamed-genblk
2021-02-03 whitequarkMerge pull request #2436 from dalance/fix_generate
2021-01-31 Zachary Snowverilog: significant block scoping improvements
2021-01-29 whitequarkMerge pull request #2564 from whitequark/flatten-improv...
2021-01-28 Claire XenMerge pull request #2535 from Ravenslofty/scc-specify
2021-01-26 Marcelina Kościelnickaxilinx_dffopt: Don't crash on missing IS_*_INVERTED.
2021-01-26 Marcelina Kościelnickaxilinx: Add FDRSE_1, FDCPE_1.
2021-01-04 whitequarkMerge pull request #2522 from tomverbeure/simlib_typos2
2021-01-04 Tom VerbeureFix some trivial typos.
2021-01-01 whitequarkMerge pull request #2480 from YosysHQ/dave/nexus-lram
2020-12-23 whitequarkMerge pull request #2476 from zachjs/const-arg-width
2020-12-22 whitequarkMerge pull request #2497 from whitequark/cxxrtl-reflow
2020-12-22 whitequarkMerge pull request #2479 from zachjs/const-arg-hint
2020-12-22 whitequarkMerge pull request #2491 from zachjs/port-bind-sign
2020-12-21 Marcelina Kościelnickaxilinx: Add some missing blackbox cells.
2020-12-21 Marcelina Kościelnickaxilinx: Regenerate cells_xtra.v using Vivado 2020.2
2020-12-19 whitequarkMerge pull request #2487 from whitequark/cxxrtl-outlining
2020-12-17 Marcelina Kościelnickaxilinx: Add FDDRCPE and FDDRRSE blackbox cells.
2020-12-08 David Shahnexus: Add MULTADDSUB9X9WIDE sim model
2020-12-07 David Shahnexus: Add LRAM inference
2020-12-02 whitequarkMerge pull request #2468 from whitequark/cxxrtl-assert
2020-12-02 whitequarkMerge pull request #2469 from whitequark/cxxrtl-no-clk
2020-12-02 whitequarkMerge pull request #2466 from whitequark/cxxrtl-reset
2020-12-02 whitequarkMerge pull request #2456 from Zottel/master
2020-12-02 whitequarkMerge pull request #2455 from gsomlo/gls-fedpkg-fixes
2020-12-02 David ShahMerge pull request #2467 from YosysHQ/dave/nexus-carry-fix
2020-12-02 whitequarkMerge pull request #2446 from RobertBaruch/rtlil_format
2020-12-02 David Shahnexus: More efficient CO mapping
2020-12-01 Claire XenMerge pull request #2463 from georgerennie/fix_verilog_...
2020-12-01 Miodrag MilanovićMerge pull request #2460 from pepijndevos/simple-gowin
2020-11-30 Pepijn de Vosadd -noalu and -json option for apicula
2020-11-25 whitequarkMerge pull request #2452 from whitequark/rtlil-remove...
2020-11-25 Claire XenMerge pull request #2133 from dh73/nodev_head
2020-11-25 whitequarkMerge pull request #2442 from cr1901/sccache
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