Merge pull request #871 from YosysHQ/verific_import
[yosys.git] / techlibs /
2019-05-06 Clifford WolfMerge pull request #871 from YosysHQ/verific_import
2019-05-03 Eddie HungRename cells_map.v to prevent clash with ff_map.v
2019-05-03 Clifford WolfMerge pull request #969 from YosysHQ/clifford/pmgenstuff
2019-05-03 Eddie HungRevert "synth_xilinx to call dffinit with -noreinit"
2019-05-03 Clifford WolfMerge pull request #976 from YosysHQ/clifford/fix974
2019-05-03 Eddie Hungsynth_xilinx to call dffinit with -noreinit
2019-05-02 Clifford WolfMerge pull request #963 from YosysHQ/eddie/synth_xilinx...
2019-05-02 Eddie HungBack to passing all xc7srl tests!
2019-05-02 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-05-01 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-04-30 Clifford WolfMerge pull request #972 from YosysHQ/clifford/fix968
2019-04-30 Clifford WolfMerge pull request #966 from YosysHQ/clifford/fix956
2019-04-30 Clifford WolfMerge pull request #962 from YosysHQ/eddie/refactor_syn...
2019-04-30 Clifford WolfMerge branch 'master' into eddie/refactor_synth_xilinx
2019-04-30 Clifford WolfAdd handling of init attributes in "opt_expr -undriven"
2019-04-30 Benedikt TutzerMerge branch 'master' of https://github.com/YosysHQ...
2019-04-30 Clifford WolfRun "peepopt" in generic "synth" pass and "synth_ice40"
2019-04-29 Clifford WolfMerge pull request #960 from YosysHQ/eddie/equiv_opt_undef
2019-04-28 Eddie HungWIP
2019-04-28 Eddie HungMove neg-pol to pos-pol mapping from ff_map to cells_map.v
2019-04-26 Eddie HungRevert synth_xilinx 'fine' label more to how it used...
2019-04-26 Eddie HungWhere did this check come from!?!
2019-04-26 Eddie HungRefactor synth_xilinx to auto-generate doc
2019-04-26 Eddie HungCleanup ice40
2019-04-22 Eddie HungMerge pull request #914 from YosysHQ/xc7srl
2019-04-22 Eddie HungUpdate help message
2019-04-22 Eddie HungMove 'shregmap -tech xilinx' into map_cells
2019-04-22 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-22 Clifford WolfMerge pull request #905 from christian-krieg/feature...
2019-04-22 Clifford WolfMerge pull request #941 from Wren6991/sim_lib_io_clke
2019-04-22 Clifford WolfMerge branch 'dh73-master'
2019-04-22 Clifford WolfMerge branch 'master' of https://github.com/dh73/yosys_...
2019-04-22 Clifford WolfRe-added clean after techmap in synth_xilinx
2019-04-22 Clifford WolfMerge pull request #916 from YosysHQ/map_cells_before_m...
2019-04-22 Clifford WolfMerge pull request #911 from mmicko/gowin-nobram
2019-04-22 Clifford WolfMerge pull request #909 from zachjs/master
2019-04-21 Eddie HungTidy up, fix for -nosrl
2019-04-21 Eddie HungMerge branch 'map_cells_before_map_luts' into xc7srl
2019-04-21 Eddie HungMerge branch 'master' into map_cells_before_map_luts
2019-04-21 Eddie HungAdd comments
2019-04-21 Eddie HungUse new pmux2shiftx from #944, remove my old attempt
2019-04-21 Luke Wrenice40 cells_sim.v: SB_IO: update clock enable behaviour...
2019-04-21 Eddie HungMerge remote-tracking branch 'origin/clifford/pmux2shif...
2019-04-21 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-20 Clifford WolfMerge pull request #943 from YosysHQ/clifford/whitebox
2019-04-20 Eddie HungMerge remote-tracking branch 'origin/pmux2shiftx' into...
2019-04-20 Eddie HungMerge remote-tracking branch 'origin' into xc7srl
2019-04-20 Clifford WolfMerge pull request #942 from YosysHQ/clifford/fix931
2019-04-18 Eddie HungMerge pull request #917 from YosysHQ/eddie/fix_retime
2019-04-18 Eddie HungRevert "synth_* with -retime option now calls abc with...
2019-04-18 Eddie HungMerge branch 'master' into eddie/fix_retime
2019-04-13 DiegoGoWin enablement: DRAM, initial BRAM, DRAM init, DRAM...
2019-04-12 Eddie HungMerge pull request #928 from litghost/add_xc7_sim_models
2019-04-12 Keith RothmanRemove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
2019-04-12 Clifford WolfMerge pull request #933 from dh73/master
2019-04-12 DiegoFixing issues in CycloneV cell sim
2019-04-10 Eddie Hungsynth_* with -retime option now calls abc with -D 1...
2019-04-10 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-04-09 Keith RothmanFix LUT6_2 definition.
2019-04-09 Keith RothmanAdd additional cells sim models for core 7-series prima...
2019-04-08 Eddie HungMerge branch 'undo_pr895' into xc7srl
2019-04-06 Eddie HungCall shregmap twice -- once for variable, another for...
2019-04-05 Eddie HungMerge branch 'eddie/fix_retime' into xc7srl
2019-04-05 Eddie HungMove dffinit til after abc
2019-04-05 Eddie HungMerge branch 'eddie/fix_retime' into xc7srl
2019-04-05 Eddie HungMove techamp t:$_DFF_?N? to before abc call
2019-04-05 Eddie HungRetry
2019-04-05 Eddie HungResolve @daveshah1 comment, update synth_xilinx help
2019-04-05 Eddie Hungsynth_xilinx to techmap FFs after abc call, otherwise...
2019-04-05 Eddie Hungtechmap inside map_cells stage
2019-04-04 Eddie HungMerge branch 'map_cells_before_map_luts' into xc7srl
2019-04-04 Eddie HungMissing techmap entry in help
2019-04-04 Eddie HungUse soft-logic, not LUT3 instantiation
2019-04-04 Eddie HungMerge branch 'map_cells_before_map_luts' into xc7srl
2019-04-04 Eddie Hungsynth_xilinx to map_cells before map_luts
2019-04-04 Eddie HungCleanup comments
2019-04-04 Eddie Hungt:$dff* -> t:$dff t:$dffe
2019-04-03 Eddie Hung-nosrl meant when -nobram
2019-04-03 Eddie HungRemove duplicate STARTUPE2
2019-04-03 Eddie HungDisable shregmap in synth_xilinx if -retime
2019-04-03 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-02 Miodrag MilanovicMake nobram false by default for gowin
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2019-03-25 Eddie Hungsynth_xilinx to use shregmap with -minlen 3
2019-03-25 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-22 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-22 Clifford WolfMerge pull request #889 from YosysHQ/clifford/fix888
2019-03-22 Clifford WolfMerge pull request #890 from YosysHQ/clifford/fix887
2019-03-22 David ShahMerge pull request #891 from YosysHQ/xilinx_keep
2019-03-22 David Shahxilinx: Add keep attribute where appropriate
2019-03-21 Eddie HungAdd '-nosrl' option to synth_xilinx
2019-03-20 Eddie HungFine tune cells_map.v
2019-03-20 Eddie HungRevert $__SHREG_ to orig; use $__XILINX_SHREG for varia...
2019-03-20 Eddie HungAdd support for variable length Xilinx SRL > 128
2019-03-19 Eddie HungRestore original synth_xilinx commands
2019-03-19 Eddie HungFix spacing
2019-03-19 Eddie HungFix INIT for variable length SRs that have been bumped...
2019-03-19 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-19 Clifford WolfMerge pull request #885 from YosysHQ/clifford/fix873
2019-03-19 Clifford WolfAdd Xilinx negedge FFs to synth_xilinx dffinit call...
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