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examples/anlogic/ now also output the SVF file.
[yosys.git] / techlibs /
2018-12-06 Olof KindgrenOnly use non-blocking assignments of SB_RAM40_4K for... tree | commitdiff
2018-12-06 whitequarksynth_ice40: split `map_gates` off `fine`. tree | commitdiff
2018-12-05 Clifford WolfMerge pull request #709 from smunaut/issue_708 tree | commitdiff
2018-12-05 Clifford WolfMerge pull request #718 from whitequark/gate2lut tree | commitdiff
2018-12-05 whitequarksynth_ice40: add -noabc option, to use built-in LUT... tree | commitdiff
2018-12-05 whitequarkgate2lut: new techlib, for converting Yosys gates to... tree | commitdiff
2018-12-05 whitequarkFix typo. tree | commitdiff
2018-12-05 Clifford WolfMerge pull request #713 from Diego-HR/master tree | commitdiff
2018-12-05 Clifford WolfMerge pull request #712 from mmicko/anlogic-support tree | commitdiff
2018-12-05 Clifford WolfMerge pull request #717 from whitequark/opt_lut tree | commitdiff
2018-12-05 Clifford WolfMerge pull request #716 from whitequark/ice40_unlut tree | commitdiff
2018-12-05 whitequarkopt_lut: add -dlogic, to avoid disturbing logic such... tree | commitdiff
2018-12-05 whitequarksynth_ice40: add -relut option, to run ice40_unlut... tree | commitdiff
2018-12-05 whitequarkExtract ice40_unlut pass from ice40_opt. tree | commitdiff
2018-12-04 Clifford WolfMerge pull request #702 from smunaut/min_ce_use tree | commitdiff
2018-12-04 Diego HChanges in GoWin synth commands and ALU primitive support tree | commitdiff
2018-12-02 Miodrag MilanovicLeave only real black box cells tree | commitdiff
2018-12-01 Miodrag MilanovicInitial support for Anlogic FPGA tree | commitdiff
2018-12-01 Clifford WolfMerge pull request #676 from rafaeltp/master tree | commitdiff
2018-11-27 Sylvain Munautice40: Add option to only use CE if it'd be use by... tree | commitdiff
2018-11-12 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys tree | commitdiff
2018-11-12 Clifford WolfMerge pull request #697 from eddiehung/xilinx_ps7 tree | commitdiff
2018-11-12 Clifford WolfMerge pull request #695 from daveshah1/ecp5_bb tree | commitdiff
2018-11-10 Eddie HungAdd support for Xilinx PS7 block tree | commitdiff
2018-11-09 David Shahecp5: Add 'fake' DCU parameters tree | commitdiff
2018-11-09 David Shahecp5: Add blackboxes for ancillary DCU cells tree | commitdiff
2018-11-07 David Shahecp5: Adding some blackbox cells tree | commitdiff
2018-10-31 Clifford WolfMerge branch 'igloo2' tree | commitdiff
2018-10-31 Clifford WolfFix sf2 LUT interface tree | commitdiff
2018-10-31 Clifford WolfBasic SmartFusion2 and IGLOO2 synthesis support tree | commitdiff
2018-10-25 Clifford WolfMerge pull request #678 from whentze/master tree | commitdiff
2018-10-25 Clifford WolfMerge pull request #679 from udif/pr_syntax_error tree | commitdiff
2018-10-23 Clifford WolfMerge pull request #677 from daveshah1/ecp5_dsp tree | commitdiff
2018-10-22 David Shahecp5: Remove DSP parameters that don't work tree | commitdiff
2018-10-21 David Shahecp5: Add DSP blackboxes tree | commitdiff
2018-10-21 rafaeltpMerge pull request #1 from YosysHQ/master tree | commitdiff
2018-10-19 Clifford WolfMerge pull request #673 from daveshah1/ecp5_improve tree | commitdiff
2018-10-19 David Shahecp5: Sim model fixes tree | commitdiff
2018-10-19 David Shahecp5: Add latch inference tree | commitdiff
2018-10-19 Clifford WolfMerge pull request #672 from daveshah1/fix_bram tree | commitdiff
2018-10-18 Clifford WolfMerge pull request #659 from rubund/sv_interfaces tree | commitdiff
2018-10-18 Clifford WolfMerge pull request #657 from mithro/xilinx-vpr tree | commitdiff
2018-10-18 Clifford WolfMerge pull request #664 from tklam/ignore-verilog-protect tree | commitdiff
2018-10-17 Clifford WolfMerge pull request #660 from tklam/parse-liberty-detect... tree | commitdiff
2018-10-17 Clifford WolfMerge pull request #663 from aman-goel/master tree | commitdiff
2018-10-17 Clifford WolfMerge pull request #658 from daveshah1/ecp5_bram tree | commitdiff
2018-10-17 Clifford WolfMerge pull request #638 from udif/pr_reg_wire_error tree | commitdiff
2018-10-16 Clifford WolfMerge branch 'yosys-0.8-rc' tree | commitdiff
2018-10-16 David Shahecp5: Disable LSR inversion tree | commitdiff
2018-10-13 tklamMerge branch 'master' of https://github.com/YosysHQ... tree | commitdiff
2018-10-12 David ShahBRAM improvements tree | commitdiff
2018-10-10 David Shahecp5: Adding BRAM maps for all size options tree | commitdiff
2018-10-10 David Shahecp5: First BRAM type maps successfully tree | commitdiff
2018-10-10 David Shahecp5: Script for BRAM IO connections tree | commitdiff
2018-10-09 David Shahecp5: Adding BRAM initialisation and config tree | commitdiff
2018-10-08 Tim 'mithro' Ansellxilinx: Still map LUT7/LUT8 to Xilinx specific primitives. tree | commitdiff
2018-10-05 David Shahecp5: Add blackbox for DP16KD tree | commitdiff
2018-10-05 Clifford WolfMerge pull request #651 from ARandomOWL/stdcells_fix tree | commitdiff
2018-10-04 Clifford WolfAdd inout ports to cells_xtra.v tree | commitdiff
2018-10-04 Clifford WolfMerge pull request #650 from mithro/patch-1 tree | commitdiff
2018-10-03 Tim Ansellxilinx: Adding missing inout IO port to IOBUF tree | commitdiff
2018-10-03 tklamMerge branch 'master' of https://github.com/YosysHQ... tree | commitdiff
2018-10-02 Clifford WolfMerge pull request #645 from daveshah1/ecp5_dram_fix tree | commitdiff
2018-10-01 David Shahecp5: Don't map ROMs to DRAM tree | commitdiff
2018-10-01 Aman GoelMerge pull request #4 from YosysHQ/master tree | commitdiff
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error tree | commitdiff
2018-09-14 Clifford WolfMerge pull request #625 from aman-goel/master tree | commitdiff
2018-09-10 Clifford WolfAdd iCE40 SB_SPRAM256KA simulation model tree | commitdiff
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master tree | commitdiff
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64 tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #576 from cr1901/no-resource tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #513 from udif/pr_reg_wire_error tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #562 from udif/pr_fix_illegal_port_decl tree | commitdiff
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in... tree | commitdiff
2018-07-18 Aman GoelMerge pull request #2 from YosysHQ/master tree | commitdiff
2018-07-16 Clifford WolfMerge pull request #581 from daveshah1/ecp5 tree | commitdiff
2018-07-16 David Shahecp5: Fixing miscellaneous sim model issues tree | commitdiff
2018-07-16 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys tree | commitdiff
2018-07-16 David Shahecp5: Fixing 'X' issues with LUT simulation models tree | commitdiff
2018-07-16 David Shahecp5: ECP5 synthesis fixes tree | commitdiff
2018-07-14 David Shahecp5: Adding synchronous set/reset support tree | commitdiff
2018-07-13 David Shahecp5: Add DRAM match rule tree | commitdiff
2018-07-13 David Shahecp5: Cells and mappings fixes tree | commitdiff
2018-07-13 David Shahecp5: Fixing arith_map tree | commitdiff
2018-07-13 David Shahecp5: Initial arith_map implementation tree | commitdiff
2018-07-13 David Shahecp5: Adding basic synth_ecp5 based on synth_ice40 tree | commitdiff
2018-07-13 David Shahecp5: Adding DFF maps tree | commitdiff
2018-07-13 Clifford WolfMerge pull request #580 from daveshah1/ice40_nx tree | commitdiff
2018-07-13 David Shahecp5: Adding DRAM map tree | commitdiff
2018-07-13 David Shahecp5: Adding basic cells_sim and mapper for LUTs up... tree | commitdiff
2018-07-13 David Shahice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC tree | commitdiff
2018-07-04 Aman GoelMerge branch 'YosysHQ-master' tree | commitdiff
2018-07-04 Aman GoelMerging with official repo tree | commitdiff
2018-06-13 Clifford WolfAdd "synth_ice40 -json" tree | commitdiff
2018-06-11 Clifford WolfFix ice40_opt for cases where a port is connected to... tree | commitdiff
2018-05-30 Clifford WolfMake -nordff the default in "prep" tree | commitdiff
2018-05-17 Clifford WolfMerge pull request #550 from jimparis/yosys-upstream tree | commitdiff
2018-05-17 Clifford WolfMerge pull request #551 from olofk/ice40_cells_sim_ports tree | commitdiff
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