Merge pull request #521 from azonenberg/for_clifford
[yosys.git] / techlibs /
2018-03-31 Clifford WolfMerge pull request #521 from azonenberg/for_clifford
2018-03-31 Robert Oucoolrunner2: Add an ANDTERM/XOR between chained FFs
2018-03-31 Robert Oucoolrunner2: Split multi-bit nets
2018-03-31 Robert Oucoolrunner2: Add extraction for TFFs
2018-03-11 Larry DoolittleSquelch trailing whitespace, including meta-whitespace
2018-03-07 Clifford WolfAdd Xilinx RAM64X1D and RAM128X1D simulation models
2018-03-04 Clifford WolfAdd "synth -noshare"
2018-02-23 Clifford WolfMerge branch 'forall'
2018-02-23 Clifford WolfAdd $allconst and $allseq cell types
2018-02-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2018-02-03 Clifford WolfMerge pull request #488 from azonenberg/for_clifford
2018-01-18 Robert Oucoolrunner2: Move LOC attributes onto the IO cells
2018-01-09 Clifford WolfAdd "dffinit -highlow" and fix synth_intel
2017-12-19 Clifford WolfFix minor typo in "prep" help message
2017-12-14 Clifford WolfMerge branch 'master' into btor-ng
2017-12-13 Clifford WolfMerge pull request #468 from grahamedgecombe/fix-sb...
2017-12-10 Graham EdgecombeFix port names in SB_IO_OD
2017-12-10 Graham EdgecombeRemove trailing comma from SB_IO_OD port list
2017-12-09 Clifford WolfMerge branch 'master' into btor-ng
2017-12-09 Clifford WolfMerge pull request #467 from mithro/patch-1
2017-12-09 Tim AnsellFix spelling in -vpr help for synth_ice40
2017-12-01 Clifford WolfMerge branch 'master' into btor-ng
2017-11-28 Clifford WolfMerge pull request #462 from daveshah1/up5k
2017-11-28 David ShahAdd remaining UltraPlus cells to ice40 techlib
2017-11-24 Clifford WolfMerge pull request #446 from mithro/travis-rework
2017-11-23 Clifford WolfMerge branch 'master' into btor-ng
2017-11-23 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-11-18 Clifford WolfMerge pull request #455 from daveshah1/up5k
2017-11-18 David ShahRemove unnecessary keep attributes
2017-11-18 Clifford WolfMerge pull request #452 from cr1901/master
2017-11-18 Clifford WolfMerge pull request #453 from dh73/master
2017-11-17 David ShahMerge branch 'master' into up5k
2017-11-16 Clifford WolfAdd "synth_ice40 -vpr"
2017-11-16 David ShahAdd some UltraPlus cells to ice40 techlib
2017-11-09 dh73Initial Cyclone 10 support
2017-11-09 dh73Merge https://github.com/cliffordwolf/yosys
2017-11-09 dh73Organizing Speedster file names
2017-10-10 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-10-05 Larry DoolittleClean whitespace and permissions in techlibs/intel
2017-10-03 Clifford WolfMerge branch 'pr_ast_const_funcs' of https://github...
2017-10-03 Clifford WolfMerge branch 'fix_shift_reduce_conflict' of https:...
2017-10-03 Clifford WolfMerge branch 'dh73-master'
2017-10-03 Clifford WolfRename "write_verilog -nobasenradix" to "write_verilog...
2017-10-02 dh73Tested and working altsyncarm without init files
2017-10-01 dh73Adding Cyclone IV (E, GX), Arria 10, Cyclone V and...
2017-09-29 Clifford WolfAdd first draft of eASIC back-end
2017-09-29 Clifford WolfFix synth_ice40 doc regarding -top default
2017-09-14 Clifford WolfMerge pull request #412 from azonenberg/reduce-fixes
2017-09-14 Clifford WolfMerge pull request #411 from azonenberg/counter-extract...
2017-09-14 Andrew ZonenbergAdded RESET_TO_MAX parameter to $__COUNT_ cell. Cannot...
2017-09-14 Andrew ZonenbergInitial support for extraction of counters with clock...
2017-09-02 Clifford WolfMerge pull request #406 from azonenberg/coolrunner...
2017-09-02 Clifford WolfMerge pull request #405 from azonenberg/gpak-refactoring
2017-09-01 Robert Oucoolrunner2: Finish fixing special-use p-terms
2017-09-01 Robert Oucoolrunner2: Generate a feed-through AND term when...
2017-09-01 Robert Oucoolrunner2: Initial fixes for special p-terms
2017-09-01 Robert Oucoolrunner2: Fix mapping of flip-flops
2017-09-01 Robert Oucoolrunner2: Combine some for loops together
2017-09-01 Andrew ZonenbergFixed typo in error message
2017-09-01 Andrew ZonenbergAdded blackbox $__COUNT_ cell model
2017-09-01 Andrew ZonenbergRefactoring: moved modules still in cells_sim to cells_...
2017-09-01 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-09-01 Clifford WolfMerge branch 'ChipScan-master'
2017-08-31 Clifford WolfMerge pull request #399 from azonenberg/counter-extraction
2017-08-31 Andrew ZonenbergMerge branch 'counter-extraction' of github.com:azonenb...
2017-08-30 Andrew ZonenbergMerge branch 'master' of https://github.com/cliffordwol...
2017-08-30 Andrew Zonenbergextract_counter: Minor changes requested to comply...
2017-08-30 Jason LowdermilkMerge remote-tracking branch 'upstream/master'
2017-08-30 Clifford WolfMerge pull request #397 from azonenberg/gpak-libfixes
2017-08-29 Andrew ZonenbergFinished refactoring counter extraction to be nice...
2017-08-29 Andrew ZonenbergRefactoring: Renamed greenpak4_counters pass to extract...
2017-08-28 Andrew ZonenbergReformatted GP_COUNTx_ADV resets to avoid Yosys thinkin...
2017-08-28 Clifford WolfMerge branch 'recover-reduce' of https://github.com...
2017-08-28 Clifford WolfMerge pull request #392 from azonenberg/greenpak-portfixes
2017-08-27 Andrew ZonenbergFixed bug causing GP_SPI model to not synthesize
2017-08-18 Clifford WolfMerge branch 'sim'
2017-08-16 Clifford WolfMerge pull request #386 from azonenberg/gpak-counters
2017-08-15 Andrew ZonenbergFixed more issues with GreenPAK counter sim models
2017-08-15 Andrew ZonenbergUpdated PGEN model to have level triggered reset (match...
2017-08-15 Andrew ZonenbergFixed bug in GP_COUNTx model
2017-08-15 Andrew ZonenbergFixed bug where GP_COUNTx_ADV would wrap even when...
2017-08-15 Clifford WolfMerge branch 'rmports' of https://github.com/azonenberg...
2017-08-14 Clifford WolfMerge pull request #381 from azonenberg/countfix
2017-08-14 Clifford WolfMerge pull request #383 from azonenberg/abcfnames
2017-08-14 Clifford WolfMerge pull request #382 from azonenberg/jsoniofix
2017-08-14 Clifford WolfMerge pull request #384 from azonenberg/crtechlib
2017-08-14 Robert Oucoolrunner2: Add INVERT parameter to some BUFGs
2017-08-14 Robert Oucoolrunner2: Add FFs with clock enable to cells_sim.v
2017-08-14 Andrew ZonenbergFixed typo in GP_COUNT8 sim model
2017-08-14 Andrew ZonenbergFixed typo in error message
2017-08-14 Andrew ZonenbergChanged LEVEL resets for GP_COUNTx to be properly synth...
2017-08-14 Andrew ZonenbergChanged LEVEL resets to be edge triggered anyway
2017-08-14 Andrew ZonenbergAdded level-triggered reset support to GP_COUNTx simula...
2017-08-14 Andrew ZonenbergFixed undeclared "count" in GP_COUNT8_ADV
2017-08-14 Andrew ZonenbergFixed undeclared "count" in GP_COUNT14_ADV
2017-08-14 Andrew ZonenbergFixed typo in last commit
2017-08-14 Andrew ZonenbergFinished initial GP_COUNT8/14/8_ADV/14_ADV sim models...
2017-08-14 Andrew ZonenbergFixed typo in COUNT8 model
2017-08-14 Andrew ZonenbergMoved GP_POR out of digital cells b/c it has delays
2017-08-14 Andrew ZonenbergImproved cells_sim_digital model for GP_COUNT8
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