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Initial support for Anlogic FPGA
[yosys.git]
/
techlibs
/
2018-12-01
Miodrag Milanovic
Initial support for Anlogic FPGA
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commitdiff
2018-12-01
Clifford Wolf
Merge pull request #676 from rafaeltp/master
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commitdiff
2018-11-12
Clifford Wolf
Merge branch 'master' of github.com:YosysHQ/yosys
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2018-11-12
Clifford Wolf
Merge pull request #697 from eddiehung/xilinx_ps7
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2018-11-12
Clifford Wolf
Merge pull request #695 from daveshah1/ecp5_bb
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2018-11-10
Eddie Hung
Add support for Xilinx PS7 block
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commitdiff
2018-11-09
David Shah
ecp5: Add 'fake' DCU parameters
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commitdiff
2018-11-09
David Shah
ecp5: Add blackboxes for ancillary DCU cells
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commitdiff
2018-11-07
David Shah
ecp5: Adding some blackbox cells
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commitdiff
2018-10-31
Clifford Wolf
Merge branch 'igloo2'
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commitdiff
2018-10-31
Clifford Wolf
Fix sf2 LUT interface
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commitdiff
2018-10-31
Clifford Wolf
Basic SmartFusion2 and IGLOO2 synthesis support
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commitdiff
2018-10-25
Clifford Wolf
Merge pull request #678 from whentze/master
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commitdiff
2018-10-25
Clifford Wolf
Merge pull request #679 from udif/pr_syntax_error
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commitdiff
2018-10-23
Clifford Wolf
Merge pull request #677 from daveshah1/ecp5_dsp
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commitdiff
2018-10-22
David Shah
ecp5: Remove DSP parameters that don't work
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commitdiff
2018-10-21
David Shah
ecp5: Add DSP blackboxes
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commitdiff
2018-10-21
rafaeltp
Merge pull request #1 from YosysHQ/master
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commitdiff
2018-10-19
Clifford Wolf
Merge pull request #673 from daveshah1/ecp5_improve
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commitdiff
2018-10-19
David Shah
ecp5: Sim model fixes
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commitdiff
2018-10-19
David Shah
ecp5: Add latch inference
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commitdiff
2018-10-19
Clifford Wolf
Merge pull request #672 from daveshah1/fix_bram
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commitdiff
2018-10-18
Clifford Wolf
Merge pull request #659 from rubund/sv_interfaces
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commitdiff
2018-10-18
Clifford Wolf
Merge pull request #657 from mithro/xilinx-vpr
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commitdiff
2018-10-18
Clifford Wolf
Merge pull request #664 from tklam/ignore-verilog-protect
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commitdiff
2018-10-17
Clifford Wolf
Merge pull request #660 from tklam/parse-liberty-detect...
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commitdiff
2018-10-17
Clifford Wolf
Merge pull request #663 from aman-goel/master
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commitdiff
2018-10-17
Clifford Wolf
Merge pull request #658 from daveshah1/ecp5_bram
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commitdiff
2018-10-17
Clifford Wolf
Merge pull request #638 from udif/pr_reg_wire_error
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commitdiff
2018-10-16
Clifford Wolf
Merge branch 'yosys-0.8-rc'
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commitdiff
2018-10-16
David Shah
ecp5: Disable LSR inversion
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commitdiff
2018-10-13
tklam
Merge branch 'master' of https://github.com/YosysHQ...
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commitdiff
2018-10-12
David Shah
BRAM improvements
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2018-10-10
David Shah
ecp5: Adding BRAM maps for all size options
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commitdiff
2018-10-10
David Shah
ecp5: First BRAM type maps successfully
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commitdiff
2018-10-10
David Shah
ecp5: Script for BRAM IO connections
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commitdiff
2018-10-09
David Shah
ecp5: Adding BRAM initialisation and config
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commitdiff
2018-10-08
Tim 'mithro' Ansell
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.
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commitdiff
2018-10-05
David Shah
ecp5: Add blackbox for DP16KD
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commitdiff
2018-10-05
Clifford Wolf
Merge pull request #651 from ARandomOWL/stdcells_fix
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commitdiff
2018-10-04
Clifford Wolf
Add inout ports to cells_xtra.v
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commitdiff
2018-10-04
Clifford Wolf
Merge pull request #650 from mithro/patch-1
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commitdiff
2018-10-03
Tim Ansell
xilinx: Adding missing inout IO port to IOBUF
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commitdiff
2018-10-03
tklam
Merge branch 'master' of https://github.com/YosysHQ...
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commitdiff
2018-10-02
Clifford Wolf
Merge pull request #645 from daveshah1/ecp5_dram_fix
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commitdiff
2018-10-01
David Shah
ecp5: Don't map ROMs to DRAM
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commitdiff
2018-10-01
Aman Goel
Merge pull request #4 from YosysHQ/master
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commitdiff
2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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commitdiff
2018-09-14
Clifford Wolf
Merge pull request #625 from aman-goel/master
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commitdiff
2018-09-10
Clifford Wolf
Add iCE40 SB_SPRAM256KA simulation model
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commitdiff
2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
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commitdiff
2018-08-18
Aman Goel
Merge pull request #3 from YosysHQ/master
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commitdiff
2018-08-15
Clifford Wolf
Merge pull request #573 from cr1901/msys-64
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commitdiff
2018-08-15
Clifford Wolf
Merge pull request #591 from hzeller/virtual-override
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2018-08-15
Clifford Wolf
Merge pull request #576 from cr1901/no-resource
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commitdiff
2018-08-15
Clifford Wolf
Merge pull request #513 from udif/pr_reg_wire_error
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commitdiff
2018-08-15
Clifford Wolf
Merge pull request #562 from udif/pr_fix_illegal_port_decl
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commitdiff
2018-07-21
Henner Zeller
Consistent use of 'override' for virtual methods in...
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commitdiff
2018-07-18
Aman Goel
Merge pull request #2 from YosysHQ/master
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commitdiff
2018-07-16
Clifford Wolf
Merge pull request #581 from daveshah1/ecp5
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commitdiff
2018-07-16
David Shah
ecp5: Fixing miscellaneous sim model issues
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commitdiff
2018-07-16
Clifford Wolf
Merge branch 'master' of github.com:YosysHQ/yosys
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commitdiff
2018-07-16
David Shah
ecp5: Fixing 'X' issues with LUT simulation models
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2018-07-16
David Shah
ecp5: ECP5 synthesis fixes
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2018-07-14
David Shah
ecp5: Adding synchronous set/reset support
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2018-07-13
David Shah
ecp5: Add DRAM match rule
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2018-07-13
David Shah
ecp5: Cells and mappings fixes
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commitdiff
2018-07-13
David Shah
ecp5: Fixing arith_map
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commitdiff
2018-07-13
David Shah
ecp5: Initial arith_map implementation
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commitdiff
2018-07-13
David Shah
ecp5: Adding basic synth_ecp5 based on synth_ice40
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commitdiff
2018-07-13
David Shah
ecp5: Adding DFF maps
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commitdiff
2018-07-13
Clifford Wolf
Merge pull request #580 from daveshah1/ice40_nx
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commitdiff
2018-07-13
David Shah
ecp5: Adding DRAM map
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commitdiff
2018-07-13
David Shah
ecp5: Adding basic cells_sim and mapper for LUTs up...
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commitdiff
2018-07-13
David Shah
ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC
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commitdiff
2018-07-04
Aman Goel
Merge branch 'YosysHQ-master'
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commitdiff
2018-07-04
Aman Goel
Merging with official repo
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commitdiff
2018-06-13
Clifford Wolf
Add "synth_ice40 -json"
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commitdiff
2018-06-11
Clifford Wolf
Fix ice40_opt for cases where a port is connected to...
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commitdiff
2018-05-30
Clifford Wolf
Make -nordff the default in "prep"
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commitdiff
2018-05-17
Clifford Wolf
Merge pull request #550 from jimparis/yosys-upstream
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commitdiff
2018-05-17
Clifford Wolf
Merge pull request #551 from olofk/ice40_cells_sim_ports
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commitdiff
2018-05-17
Olof Kindgren
Avoid mixing module port declaration styles in ice40...
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commitdiff
2018-05-04
Clifford Wolf
Merge pull request #537 from mithro/yosys-vpr
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commitdiff
2018-04-30
Clifford Wolf
Add "synth_intel --noiopads"
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commitdiff
2018-04-18
Tim 'mithro' Ansell
Improving vpr output support.
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commitdiff
2018-04-18
Tim 'mithro' Ansell
synth_ice40: Rework the vpr blif output slightly.
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commitdiff
2018-04-16
Clifford Wolf
Add "synth_ice40 -nodffe"
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commitdiff
2018-04-01
Clifford Wolf
Merge pull request #522 from c60k28/master
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commitdiff
2018-04-01
c60k28
Fixed broken Quartus backend on dffeas init value ...
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commitdiff
2018-03-31
Clifford Wolf
Merge pull request #521 from azonenberg/for_clifford
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commitdiff
2018-03-31
Robert Ou
coolrunner2: Add an ANDTERM/XOR between chained FFs
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2018-03-31
Robert Ou
coolrunner2: Split multi-bit nets
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commitdiff
2018-03-31
Robert Ou
coolrunner2: Add extraction for TFFs
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commitdiff
2018-03-11
Larry Doolittle
Squelch trailing whitespace, including meta-whitespace
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commitdiff
2018-03-07
Clifford Wolf
Add Xilinx RAM64X1D and RAM128X1D simulation models
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2018-03-04
Clifford Wolf
Add "synth -noshare"
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2018-02-23
Clifford Wolf
Merge branch 'forall'
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2018-02-23
Clifford Wolf
Add $allconst and $allseq cell types
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commitdiff
2018-02-03
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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