Merge pull request #895 from YosysHQ/pmux2shiftx
[yosys.git] / techlibs /
2019-03-22 Clifford WolfMerge pull request #889 from YosysHQ/clifford/fix888
2019-03-22 Clifford WolfMerge pull request #890 from YosysHQ/clifford/fix887
2019-03-22 David ShahMerge pull request #891 from YosysHQ/xilinx_keep
2019-03-22 David Shahxilinx: Add keep attribute where appropriate
2019-03-19 Clifford WolfMerge pull request #885 from YosysHQ/clifford/fix873
2019-03-19 Clifford WolfAdd Xilinx negedge FFs to synth_xilinx dffinit call...
2019-03-19 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-03-14 Clifford WolfMerge pull request #869 from cr1901/win-shell
2019-03-13 Clifford WolfMerge pull request #868 from YosysHQ/clifford/fixmem
2019-03-12 Clifford WolfRemove ice40/cells_sim.v hack to avoid warning for...
2019-03-09 Clifford WolfFix typo in ice40_braminit help msg
2019-03-09 Clifford WolfMerge pull request #859 from smunaut/ice40_braminit
2019-03-07 Sylvain Munautice40: Run ice40_braminit pass by default
2019-03-07 Sylvain Munautice40: Add ice40_braminit pass to allow initialization...
2019-03-07 Clifford WolfMerge pull request #856 from kprasadvnsi/master
2019-03-07 Clifford WolfAdd link to SF2 / igloo2 macro library guide
2019-03-07 Clifford WolfImprovements in sf2 cells_sim.v
2019-03-06 Clifford WolfAdd sf2 techmap rules for more FF types
2019-03-06 Clifford WolfRefactor SF2 iobuf insertion, Add clkint insertion
2019-03-06 Clifford WolfImprovements in SF2 flow and demo
2019-03-05 Clifford WolfMerge pull request #842 from litghost/merge_upstream
2019-03-05 Clifford WolfMerge pull request #850 from daveshah1/ecp5_warn_conflict
2019-03-05 Clifford WolfMerge pull request #851 from kprasadvnsi/master
2019-03-05 Clifford WolfMerge pull request #852 from ucb-bar/firrtlfixes
2019-03-05 Clifford WolfUse "write_edif -pvector bra" for Xilinx EDIF files
2019-03-04 Keith RothmanRevert BRAM WRITE_MODE changes.
2019-03-04 David Shahecp5: Demote conflicting FF init values to a warning
2019-03-01 Keith RothmanRevert FF models to include IS_x_INVERTED parameters.
2019-03-01 Keith RothmanUse singular for disabling of DRAM or BRAM inference.
2019-03-01 Keith RothmanModify arguments to match existing style.
2019-03-01 Keith RothmanChanges required for VPR place and route synth_xilinx.
2019-03-01 Clifford WolfMerge pull request #841 from mmicko/master
2019-03-01 Miodrag MilanovicFix ECP5 cells_sim for iverilog
2019-03-01 Clifford WolfMerge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
2019-03-01 Elmsice40: use 2 bits for READ/WRITE MODE for SB_RAM map
2019-02-28 Larry DoolittleReduce amount of trailing whitespace in code base
2019-02-28 Clifford WolfMerge pull request #794 from daveshah1/ecp5improve
2019-02-28 Clifford WolfMerge pull request #827 from ucb-bar/firrtlfixes
2019-02-26 Larry Doolittletechlibs/greenpak4/cells_map.v: Harmonize whitespace...
2019-02-26 Larry DoolittleClean up some whitepsace outliers
2019-02-25 David Shahecp5: Compatibility with Migen AsyncResetSynchronizer
2019-02-24 Clifford WolfMerge pull request #812 from ucb-bar/arrayhierarchyfixes
2019-02-24 Clifford WolfMerge pull request #824 from litghost/fix_reduce_on_ff
2019-02-22 Clifford WolfMerge pull request #819 from YosysHQ/clifford/optd
2019-02-22 Clifford WolfMerge pull request #820 from YosysHQ/clifford/fix810
2019-02-22 Clifford WolfMerge pull request #740 from daveshah1/improve_dress
2019-02-21 Clifford WolfMerge pull request #818 from YosysHQ/clifford/dffsrfix
2019-02-21 Clifford WolfMerge pull request #786 from YosysHQ/pmgen
2019-02-21 Clifford WolfBugfix in ice40_dsp
2019-02-20 Clifford WolfAdd ice40 test_dsp_map test case generator
2019-02-20 Clifford WolfAdd "synth_ice40 -dsp"
2019-02-20 Clifford WolfImprove iCE40 SB_MAC16 model
2019-02-19 David Shahecp5: Add DDRDLLA
2019-02-19 David Shahecp5: Add DELAYF/DELAYG blackboxes
2019-02-19 Clifford WolfAdd first draft of functional SB_MAC16 model
2019-02-18 Eddie HungMerge branch 'dff_init' into read_aiger
2019-02-17 Eddie HungRevert "Add INIT parameter to all ff/latch cells"
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into dff_init
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-02-17 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-02-13 David Shahecp5: Add ECLKSYNCB blackbox
2019-02-12 David Shahecp5: Full set of IO-related blackboxes
2019-02-08 Eddie HungMerge remote-tracking branch 'origin/dff_init' into...
2019-02-06 Eddie HungCope WIDTH of ff/latch cells is default of zero
2019-02-06 Eddie HungMerge branch 'dff_init' of https://github.com/eddiehung...
2019-02-06 Eddie HungAdd INIT parameter to all ff/latch cells
2019-02-06 David Shahecp5: Use abc -dress
2019-02-06 David Shahice40: Use abc -dress in synth_ice40
2019-01-27 Clifford WolfMerge pull request #798 from mmicko/master
2019-01-25 Miodrag MilanovicFixed Anlogic simulation model
2019-01-22 David Shahecp5: Support for flipflop initialisation
2019-01-21 David Shahecp5: Add LSRMODE to flipflops for PRLD support
2019-01-21 David Shahecp5: More blackboxes
2019-01-21 David Shahecp5: Increase threshold for ALU mapping
2019-01-17 Clifford WolfAdd SF2 IO buffer insertion
2019-01-17 Clifford WolfAdd "synth_sf2 -vlog", fix "synth_sf2 -edif"
2019-01-07 Clifford WolfMerge pull request #782 from whitequark/flowmap_dfs
2019-01-04 Clifford WolfMerge pull request #777 from mmicko/achronix_cell_sim_fix
2019-01-04 Miodrag MilanovicFix cells_sim.v for Achronix FPGA
2019-01-04 Clifford WolfMerge pull request #776 from mmicko/unify_noflatten
2019-01-04 Miodrag MilanovicUnify usage of noflatten among architectures
2019-01-02 Clifford WolfMerge pull request #770 from whitequark/opt_expr_cmp
2019-01-02 Clifford WolfMerge pull request #755 from Icenowy/anlogic-dram-init
2019-01-02 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys
2019-01-02 Clifford WolfMerge pull request #750 from Icenowy/anlogic-ff-init
2019-01-02 Clifford WolfMerge pull request #773 from whitequark/opt_lut_elim_fixes
2019-01-02 Clifford WolfMerge pull request #772 from whitequark/synth_lut
2019-01-02 Clifford WolfMerge pull request #771 from whitequark/techmap_cmp2lut
2019-01-02 Clifford WolfMerge pull request #769 from whitequark/typos
2019-01-02 whitequarkFix typographical and grammatical errors and inconsiste...
2019-01-02 whitequarksynth_ice40: use 4-LUT coarse synthesis mode.
2019-01-02 whitequarksynth: add k-LUT mode.
2019-01-02 whitequarksynth: improve script documentation. NFC.
2019-01-02 whitequarkcmp2lut: new techmap pass.
2018-12-31 Clifford WolfMerge pull request #766 from Icenowy/anlogic-latches
2018-12-29 Larry DoolittleFix 7 instances of add_share_file to add_gen_share_file
2018-12-25 Icenowy Zhenganlogic: add latch cells
2018-12-23 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys
2018-12-22 Clifford WolfMerge pull request #757 from whitequark/manual_mem
2018-12-19 Icenowy Zhenganlogic: implement DRAM initialization
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