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Fixed keep attribute on wires in opt_clean
[yosys.git] / techlibs /
2013-11-06 Clifford WolfFixed techmap of $reduce_xnor with multi-bit outputs tree | commitdiff
2013-11-06 Clifford WolfFixed techmap of $gt and $ge with multi-bit outputs tree | commitdiff
2013-11-06 Clifford WolfImproved width extension with regard to undef propagation tree | commitdiff
2013-11-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys tree | commitdiff
2013-10-31 Clifford WolfAdded DFFSR cell to techlibs/cmos/cmos_cells.lib tree | commitdiff
2013-10-27 Clifford WolfMerge pull request #12 from jameswalmsley/master tree | commitdiff
2013-10-27 James Walmsley[EXAMPLES] Ported the mojo counter example to Zynq... tree | commitdiff
2013-10-27 Clifford WolfCleanups in xilinx examples tree | commitdiff
2013-10-27 Clifford WolfAdded synth_xilinx command tree | commitdiff
2013-10-27 Clifford WolfMoved simple xilinx counter sim example to subdir tree | commitdiff
2013-10-27 Clifford WolfXilinx mojo_counter example is now working tree | commitdiff
2013-10-26 Clifford WolfRenamed techlibs/xilinx7 to techlibs/xilinx tree | commitdiff
2013-10-26 Clifford WolfImproved xilinx mojo_counter example tree | commitdiff
2013-10-26 Clifford WolfAdded another xilinx example (not funcional yet) tree | commitdiff
2013-10-18 Clifford WolfBugfix in dffsr techmap rules tree | commitdiff
2013-10-18 Clifford WolfAdded techmap rules for $sr, $dffsr and $dlatch tree | commitdiff
2013-10-18 Clifford WolfAdded $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_... tree | commitdiff
2013-10-18 Clifford WolfAdded $sr, $dffsr and $dlatch cell types tree | commitdiff
2013-10-16 Clifford WolfAdded map, par and bitgen to xlinx7 example tree | commitdiff
2013-09-15 Clifford WolfMoved common techlib files to techlibs/common tree | commitdiff
2013-09-14 Clifford WolfAdded spice testbench to techlibs/cmos tree | commitdiff
2013-09-14 Clifford WolfAdded spice backend tree | commitdiff
2013-09-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys tree | commitdiff
2013-08-27 Clifford WolfAdded mapping to techlibs/xilinx7 testbench (exposes... tree | commitdiff
2013-08-22 Clifford WolfAdded simple xilinx7 technology mapping files tree | commitdiff
2013-08-15 Clifford WolfImplemented same div-by-zero behavior as found in other... tree | commitdiff
2013-08-09 Clifford WolfAdded $div and $mod technology mapping tree | commitdiff
2013-07-23 Clifford WolfAdded $lut cells and abc lut mapping support tree | commitdiff
2013-07-09 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys tree | commitdiff
2013-07-09 Clifford WolfFixed shift ops with large right hand side tree | commitdiff
2013-06-13 Clifford WolfMore fixes for bugs found using xsthammer tree | commitdiff
2013-06-10 Clifford WolfMore sign-extension related fixes tree | commitdiff
2013-06-03 Clifford WolfImplemented technology mapping for multipliers (using... tree | commitdiff
2013-05-16 Clifford WolfMerge branch 'bugfix' tree | commitdiff
2013-04-07 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys tree | commitdiff
2013-04-07 Clifford WolfFixed clock related parameter names for $memrd and... tree | commitdiff
2013-03-28 Clifford WolfAdded EXTRA_TARGETS Makefile variable tree | commitdiff
2013-03-26 Clifford WolfTiny bugfix in simlib.v tree | commitdiff
2013-03-24 Clifford WolfFixed stdcells.v for $adff with undef reset value tree | commitdiff
2013-03-14 Clifford WolfMore support code for $sr cells tree | commitdiff
2013-01-05 Clifford Wolfadded .gitignore files tree | commitdiff
2013-01-05 Clifford Wolfinitial import tree | commitdiff