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Fixed keep attribute on wires in opt_clean
[yosys.git]
/
techlibs
/
2013-11-06
Clifford Wolf
Fixed techmap of $reduce_xnor with multi-bit outputs
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commitdiff
2013-11-06
Clifford Wolf
Fixed techmap of $gt and $ge with multi-bit outputs
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commitdiff
2013-11-06
Clifford Wolf
Improved width extension with regard to undef propagation
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commitdiff
2013-11-03
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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commitdiff
2013-10-31
Clifford Wolf
Added DFFSR cell to techlibs/cmos/cmos_cells.lib
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commitdiff
2013-10-27
Clifford Wolf
Merge pull request #12 from jameswalmsley/master
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commitdiff
2013-10-27
James Walmsley
[EXAMPLES] Ported the mojo counter example to Zynq...
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commitdiff
2013-10-27
Clifford Wolf
Cleanups in xilinx examples
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commitdiff
2013-10-27
Clifford Wolf
Added synth_xilinx command
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commitdiff
2013-10-27
Clifford Wolf
Moved simple xilinx counter sim example to subdir
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commitdiff
2013-10-27
Clifford Wolf
Xilinx mojo_counter example is now working
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commitdiff
2013-10-26
Clifford Wolf
Renamed techlibs/xilinx7 to techlibs/xilinx
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commitdiff
2013-10-26
Clifford Wolf
Improved xilinx mojo_counter example
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commitdiff
2013-10-26
Clifford Wolf
Added another xilinx example (not funcional yet)
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commitdiff
2013-10-18
Clifford Wolf
Bugfix in dffsr techmap rules
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commitdiff
2013-10-18
Clifford Wolf
Added techmap rules for $sr, $dffsr and $dlatch
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commitdiff
2013-10-18
Clifford Wolf
Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_...
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commitdiff
2013-10-18
Clifford Wolf
Added $sr, $dffsr and $dlatch cell types
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commitdiff
2013-10-16
Clifford Wolf
Added map, par and bitgen to xlinx7 example
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commitdiff
2013-09-15
Clifford Wolf
Moved common techlib files to techlibs/common
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commitdiff
2013-09-14
Clifford Wolf
Added spice testbench to techlibs/cmos
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commitdiff
2013-09-14
Clifford Wolf
Added spice backend
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commitdiff
2013-09-03
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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commitdiff
2013-08-27
Clifford Wolf
Added mapping to techlibs/xilinx7 testbench (exposes...
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commitdiff
2013-08-22
Clifford Wolf
Added simple xilinx7 technology mapping files
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commitdiff
2013-08-15
Clifford Wolf
Implemented same div-by-zero behavior as found in other...
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commitdiff
2013-08-09
Clifford Wolf
Added $div and $mod technology mapping
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commitdiff
2013-07-23
Clifford Wolf
Added $lut cells and abc lut mapping support
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commitdiff
2013-07-09
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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commitdiff
2013-07-09
Clifford Wolf
Fixed shift ops with large right hand side
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commitdiff
2013-06-13
Clifford Wolf
More fixes for bugs found using xsthammer
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commitdiff
2013-06-10
Clifford Wolf
More sign-extension related fixes
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commitdiff
2013-06-03
Clifford Wolf
Implemented technology mapping for multipliers (using...
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commitdiff
2013-05-16
Clifford Wolf
Merge branch 'bugfix'
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commitdiff
2013-04-07
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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commitdiff
2013-04-07
Clifford Wolf
Fixed clock related parameter names for $memrd and...
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commitdiff
2013-03-28
Clifford Wolf
Added EXTRA_TARGETS Makefile variable
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commitdiff
2013-03-26
Clifford Wolf
Tiny bugfix in simlib.v
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commitdiff
2013-03-24
Clifford Wolf
Fixed stdcells.v for $adff with undef reset value
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commitdiff
2013-03-14
Clifford Wolf
More support code for $sr cells
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commitdiff
2013-01-05
Clifford Wolf
added .gitignore files
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commitdiff
2013-01-05
Clifford Wolf
initial import
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commitdiff