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Add #1598 testcase
[yosys.git] / techlibs /
2019-12-25 Marcin KościelnickiMerge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen tree | commitdiff
2019-12-23 Marcin Kościelnickixilinx: Test our DSP48A/DSP48A1 simulation models. tree | commitdiff
2019-12-22 Marcin Kościelnickixilinx_dsp: Initial DSP48A/DSP48A1 support. tree | commitdiff
2019-12-20 Eddie HungMerge pull request #1588 from YosysHQ/eddie/xaiger_cleanup tree | commitdiff
2019-12-20 Eddie HungAdd abc9_arrival times for RAM{32,64}M tree | commitdiff
2019-12-20 Eddie HungAdd RAM{32,64}M to abc9_map.v tree | commitdiff
2019-12-20 Eddie HungMerge pull request #1585 from YosysHQ/eddie/fix_abc9_lut tree | commitdiff
2019-12-20 Eddie HungMerge pull request #1587 from YosysHQ/revert-1558-eddie... tree | commitdiff
2019-12-20 Eddie HungRevert "Optimise write_xaiger" tree | commitdiff
2019-12-19 Eddie HungMerge pull request #1581 from YosysHQ/clifford/fix1565 tree | commitdiff
2019-12-19 Eddie HungMerge pull request #1558 from YosysHQ/eddie/xaiger_cleanup tree | commitdiff
2019-12-19 Eddie HungMerge pull request #1569 from YosysHQ/eddie/fix_1531 tree | commitdiff
2019-12-19 Eddie HungMerge pull request #1571 from YosysHQ/eddie/fix_1570 tree | commitdiff
2019-12-19 Marcin Kościelnickixilinx: Add simulation models for remaining CLB primitives. tree | commitdiff
2019-12-19 Marcin Kościelnickixilinx_dffopt: Keep order of LUT inputs. tree | commitdiff
2019-12-18 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys tree | commitdiff
2019-12-18 David ShahMerge pull request #1563 from YosysHQ/dave/async-prld tree | commitdiff
2019-12-18 Eddie HungMerge pull request #1572 from nakengelhardt/scratchpad_pass tree | commitdiff
2019-12-18 Marcin Kościelnickixilinx: Add xilinx_dffopt pass (#1557) tree | commitdiff
2019-12-18 Marcin Kościelnickixilinx: Improve flip-flop handling. tree | commitdiff
2019-12-17 Eddie HungMerge pull request #1574 from YosysHQ/eddie/xilinx_lutram tree | commitdiff
2019-12-17 Eddie HungMerge pull request #1521 from dh73/diego/memattr tree | commitdiff
2019-12-16 Eddie HungAdd unconditional match blocks for force RAM tree | commitdiff
2019-12-16 Eddie HungUpdate xc7/xcu bram rules tree | commitdiff
2019-12-16 Eddie HungMerge branch 'diego/memattr' of https://github.com... tree | commitdiff
2019-12-16 Eddie HungMerge branch 'eddie/xilinx_lutram' of github.com:YosysH... tree | commitdiff
2019-12-16 Eddie HungPopulate DID/DOD even if unused tree | commitdiff
2019-12-16 Eddie HungRename *RAM{32,64}M rules to RAM{32X2,64X1}Q tree | commitdiff
2019-12-16 Diego HRemoving fixed attribute value to !ramstyle rules tree | commitdiff
2019-12-16 Diego HMerging attribute rules into a single match block;... tree | commitdiff
2019-12-16 Eddie HungMerge pull request #1575 from rodrigomelo9/master tree | commitdiff
2019-12-16 Eddie HungMerge pull request #1577 from gromero/for-yosys tree | commitdiff
2019-12-13 Diego HRefactoring memory attribute matching based on IEEE... tree | commitdiff
2019-12-13 Eddie HungMerge pull request #1533 from dh73/bram_xilinx tree | commitdiff
2019-12-13 Eddie HungDisable RAM16X1D match rule; carry-over from LUT4 arches tree | commitdiff
2019-12-13 Eddie HungRAM64M8 to also have [5:0] for address tree | commitdiff
2019-12-13 Eddie HungAdd RAM32X6SDP and RAM64X3SDP modes tree | commitdiff
2019-12-13 Eddie HungFix RAM64M model to have 6 bit address bus tree | commitdiff
2019-12-13 Eddie HungAdd memory rules for RAM16X1D, RAM32M, RAM64M tree | commitdiff
2019-12-12 Diego HFixing citation in xc7_xcu_brams.txt file. Fixing RAMB3... tree | commitdiff
2019-12-12 Eddie Hungabc9_map.v: fix Xilinx LUTRAM tree | commitdiff
2019-12-12 Diego HUpdating RAMB36E1 thresholds. Adding test for both... tree | commitdiff
2019-12-12 Diego HMerge https://github.com/YosysHQ/yosys into bram_xilinx tree | commitdiff
2019-12-11 Eddie HungFix bitwidth mismatch; suppresses iverilog warning tree | commitdiff
2019-12-11 David ShahMerge pull request #1564 from ZirconiumX/intel_housekeeping tree | commitdiff
2019-12-10 Dan Ravensloftsynth_intel: a10gx -> arria10gx tree | commitdiff
2019-12-10 Dan Ravensloftsynth_intel: cyclone10 -> cyclone10lp tree | commitdiff
2019-12-10 Eddie HungMerge pull request #1545 from YosysHQ/eddie/ice40_wrapc... tree | commitdiff
2019-12-09 Eddie Hungice40_opt to restore attributes/name when unwrapping tree | commitdiff
2019-12-09 Eddie HungSensitive to direct inst of $__ICE40_CARRY_WRAPPER... tree | commitdiff
2019-12-09 Eddie Hungice40_wrapcarry to really preserve attributes via ... tree | commitdiff
2019-12-07 David Shahecp5: Add support for mapping PRLD FFs tree | commitdiff
2019-12-07 Eddie Hungtechmap/aigmap of whiteboxes to occur before abc9 inste... tree | commitdiff
2019-12-05 Clifford WolfMerge pull request #1551 from whitequark/manual-cell... tree | commitdiff
2019-12-04 Marcin Kościelnickixilinx: Add tristate buffer mapping. (#1528) tree | commitdiff
2019-12-04 Marcin Kościelnickixilinx: Add models for LUTRAM cells. (#1537) tree | commitdiff
2019-12-03 Eddie Hung$__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for... tree | commitdiff
2019-12-03 Eddie Hungice40_opt to ignore (* keep *) -ed cells tree | commitdiff
2019-12-03 Clifford WolfMerge pull request #1524 from pepijndevos/gowindffinit tree | commitdiff
2019-12-03 Pepijn de VosUse -match-init to not synth contradicting init values tree | commitdiff
2019-12-02 Clifford WolfMerge pull request #1539 from YosysHQ/mwk/ilang-bounds... tree | commitdiff
2019-11-29 Miodrag MilanovićMerge pull request #1540 from YosysHQ/mwk/xilinx-bufpll tree | commitdiff
2019-11-29 Marcin Kościelnickixilinx: Add missing blackbox cell for BUFPLL. tree | commitdiff
2019-11-27 Diego HAdjusting Vivado's BRAM min bits threshold for RAMB18E1 tree | commitdiff
2019-11-27 Clifford WolfMerge pull request #1501 from YosysHQ/dave/mem_copy_attr tree | commitdiff
2019-11-26 Marcin Kościelnickixilinx: Add simulation models for IOBUF and OBUFT. tree | commitdiff
2019-11-25 Marcin Kościelnickiclkbufmap: Add support for inverters in clock path. tree | commitdiff
2019-11-25 Marcin Kościelnickixilinx: Use INV instead of LUT1 when applicable tree | commitdiff
2019-11-25 Pepijn de Vosattempt to fix formatting tree | commitdiff
2019-11-25 Pepijn de Vosgowin: add and test dff init values tree | commitdiff
2019-11-23 Eddie HungMerge pull request #1520 from pietrmar/fix-1463 tree | commitdiff
2019-11-23 Martin Pietrykacoolrunner2: remove spurious log_pop() call, fixes... tree | commitdiff
2019-11-22 Clifford WolfMerge pull request #1511 from YosysHQ/dave/always tree | commitdiff
2019-11-22 Marcin Kościelnickigowin: Add missing .gitignore entries tree | commitdiff
2019-11-19 Clifford WolfMerge pull request #1449 from pepijndevos/gowin tree | commitdiff
2019-11-19 Pepijn de VosRemove dff init altogether tree | commitdiff
2019-11-19 Marcin Kościelnickixilinx: Add simulation models for MULT18X18* and DSP48A*. tree | commitdiff
2019-11-18 Pepijn de Vosadd help for nowidelut and abc9 options tree | commitdiff
2019-11-18 whitequarkMerge pull request #1494 from whitequark/write_verilog... tree | commitdiff
2019-11-17 Clifford WolfMerge pull request #1492 from YosysHQ/dave/wreduce... tree | commitdiff
2019-11-16 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ... tree | commitdiff
2019-11-15 David Shahecp5: Use new autoname pass for better cell/net names tree | commitdiff
2019-11-14 Clifford WolfMerge pull request #1490 from YosysHQ/clifford/autoname tree | commitdiff
2019-11-14 Clifford WolfMerge pull request #1444 from btut/feature/python_wrapp... tree | commitdiff
2019-11-14 Clifford WolfMerge pull request #1465 from YosysHQ/dave/ice40_timing_sim tree | commitdiff
2019-11-14 Clifford WolfMerge branch 'label-bads-btor' of https://github.com... tree | commitdiff
2019-11-13 Clifford WolfAdd "autoname" pass and use it in "synth_ice40" tree | commitdiff
2019-11-13 whitequarkMerge pull request #1488 from whitequark/flowmap-fixes tree | commitdiff
2019-11-12 Clifford WolfMerge pull request #1484 from YosysHQ/clifford/cmp2luteqne tree | commitdiff
2019-11-11 Pepijn de Vosfix fsm test with proper clock enable polarity tree | commitdiff
2019-11-11 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ... tree | commitdiff
2019-11-11 Clifford WolfDo not map $eq and $ne in cmp2lut, only proper arithmet... tree | commitdiff
2019-11-10 Clifford WolfMerge pull request #1470 from YosysHQ/clifford/subpassdoc tree | commitdiff
2019-11-06 Pepijn de Vosfix wide luts tree | commitdiff
2019-11-06 Marcin Kościelnickisynth_xilinx: Merge blackbox primitive libraries. tree | commitdiff
2019-10-28 Pepijn de Vosadd IOBUF tree | commitdiff
2019-10-28 Pepijn de Vosadd tristate buffer and test tree | commitdiff
2019-10-28 Pepijn de VosMore formatting tree | commitdiff
2019-10-28 Pepijn de Vosreally really fix formatting maybe tree | commitdiff
2019-10-28 Pepijn de Vosundo formatting fuckup tree | commitdiff
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