Add #1598 testcase
[yosys.git] / techlibs /
2019-10-28 Pepijn de Vosadd wide luts
2019-10-28 Pepijn de Vosadd 32-bit BRAM and byte-enables
2019-10-27 Clifford WolfMerge pull request #1393 from whitequark/write_verilog...
2019-10-24 Pepijn de VosALU sim tweaks
2019-10-24 David ShahMerge pull request #1455 from YosysHQ/dave/ultrascaleplus
2019-10-23 David Shahice40: Add post-pnr ICESTORM_RAM model and fix FFs
2019-10-23 David Shahice40: Support for post-pnr timing simulation
2019-10-23 David Shahxilinx: Add URAM288 mapping for xcup
2019-10-23 David Shahxilinx: Add support for UltraScale[+] BRAM mapping
2019-10-22 Marcin Kościelnickixilinx: Support multiplier mapping for all families.
2019-10-22 Clifford WolfMerge pull request #1452 from nakengelhardt/fix_dsp_mem_reg
2019-10-21 Pepijn de Vosadd a few more missing dff
2019-10-21 Pepijn de Vosadd negedge DFF
2019-10-21 Pepijn de Vosuse ADDSUB ALU mode to remove inverters
2019-10-21 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-10-20 David Shahecp5: Pass -nomfs to abc9
2019-10-19 Miodrag MilanovićMerge pull request #1457 from xobs/python-binary-name
2019-10-19 Sean CrossMakefile: don't assume python is called `python3`
2019-10-18 Miodrag MilanovićMerge pull request #1435 from YosysHQ/mmicko/efinix
2019-10-18 Miodrag MilanovićMerge branch 'master' into mmicko/efinix
2019-10-18 Miodrag MilanovićMerge branch 'master' into mmicko/anlogic
2019-10-18 Miodrag MilanovićMerge branch 'master' into eddie/pr1352
2019-10-17 N. EngelhardtCall memory_dff before DSP mapping to reserve registers...
2019-10-16 Pepijn de Vosremove duplicate DFFR
2019-10-15 Benedikt TutzerMerge branch 'master' of https://github.com/YosysHQ...
2019-10-14 Clifford WolfMerge pull request #1448 from YosysHQ/daveshah1-sv...
2019-10-14 David ShahMerge pull request #1446 from YosysHQ/dave/ecp5-ioff
2019-10-14 Clifford WolfUse "(id)" instead of "id" for types as temporary hack
2019-10-11 David Shahecp5: Add ECLKBRIDGECS blackbox
2019-10-10 David Shahecp5: Add attrmvcp to copy syn_useioff to driving FF
2019-10-10 David Shahecp5: Set syn_useioff on IO FFs to enable packing
2019-10-10 Miodrag MilanovićMerge pull request #1445 from YosysHQ/mwk/xilinx_ibufg
2019-10-10 Marcin Kościelnickixilinx: Add simulation model for IBUFG.
2019-10-08 Eddie HungMerge pull request #1432 from YosysHQ/eddie/fix1427
2019-10-08 Eddie HungMerge pull request #1433 from YosysHQ/eddie/equiv_opt_a...
2019-10-08 Eddie HungMerge pull request #1437 from YosysHQ/eddie/abc_to_abc9
2019-10-08 Eddie HungMerge pull request #1438 from YosysHQ/eddie/xilinx_dsp_...
2019-10-05 Miodrag MilanovićMerge pull request #1436 from YosysHQ/mmicko/msvc_fix
2019-10-05 Eddie HungAdd comment on why partial multipliers are 18x18
2019-10-05 Eddie HungFix typo in check_label()
2019-10-05 Eddie HungMerge branch 'master' into eddie/abc_to_abc9
2019-10-05 Eddie HungAdd temporary `abc9 -nomfs` and use for `synth_xilinx...
2019-10-05 Eddie HungRemove DSP48E1 from *_cells_xtra.v
2019-10-04 Eddie HungRename abc_* names/attributes to more precisely be...
2019-10-04 Eddie HungPanic over. Model was elsewhere. Re-arrange for consistency
2019-10-04 Eddie HungOops
2019-10-04 Eddie HungOhmilord this wasn't added all this time!?!
2019-10-04 Miodrag MilanovicFF should be initialized to 0
2019-10-04 Miodrag MilanovicAdd missing latch mapping
2019-10-04 Miodrag MilanovicMerge branch 'SergeyDegtyar/efinix' of https://github...
2019-10-04 Miodrag MilanovicMerge branch 'SergeyDegtyar/anlogic' of https://github...
2019-10-03 Clifford WolfMerge pull request #1419 from YosysHQ/eddie/lazy_derive
2019-10-03 Clifford WolfMerge pull request #1422 from YosysHQ/eddie/aigmap_select
2019-10-03 Clifford WolfMerge pull request #1429 from YosysHQ/clifford/checkmapped
2019-10-03 David ShahMerge pull request #1425 from YosysHQ/dave/ecp5_pdp16
2019-10-01 David Shahecp5: Fix shuffle_enable port
2019-10-01 David Shahecp5: Add support for mapping 36-bit wide PDP BRAMs
2019-10-01 SergeyMerge branch 'master' into SergeyDegtyar/efinix
2019-10-01 SergeyMerge branch 'master' into SergeyDegtyar/anlogic
2019-09-30 Eddie HungMerge branch 'SergeyDegtyar/ecp5' of https://github...
2019-09-30 whitequarkMerge pull request #1406 from whitequark/connect_rpc
2019-09-30 Eddie HungMerge pull request #1397 from btut/fix/python_wrappers_...
2019-09-30 Miodrag MilanovićMerge pull request #1416 from YosysHQ/mmicko/frontend_b...
2019-09-30 Clifford WolfMerge pull request #1412 from YosysHQ/eddie/equiv_opt_a...
2019-09-30 Eddie HungAdd LDCE/LDPE sim library, remove from *cells_xtra...
2019-09-30 Marcin Kościelnickisynth_xilinx: Support latches, remove used-up FF init...
2019-09-30 Eddie HungMerge pull request #1414 from hzeller/improve-replace...
2019-09-29 Eddie HungMerge pull request #1359 from YosysHQ/xc7dsp
2019-09-29 Clifford WolfMerge pull request #1411 from aman-goel/YosysHQ-master
2019-09-28 Eddie HungFix box name
2019-09-27 Eddie HungRe-order
2019-09-27 Eddie HungMissing (* mul2dsp *) for sliceB
2019-09-27 Aman GoelMerge pull request #7 from YosysHQ/master
2019-09-27 Clifford WolfMerge pull request #1404 from YosysHQ/fix_gzip_macos
2019-09-26 Eddie HungMissing an '&'
2019-09-26 Eddie HungCombine 'flatten' & 'coarse' labels in synth_ecp5 so...
2019-09-26 Eddie HungTypo
2019-09-26 Eddie Hungselect once
2019-09-26 Eddie HungStop trying to be too smart by prematurely optimising
2019-09-26 Eddie Hungmul2dsp.v slice names
2019-09-26 Eddie HungRemove unnecessary check for A_SIGNED != B_SIGNED;...
2019-09-26 Eddie HungRevert "Remove _TECHMAP_CELLTYPE_ check since all ...
2019-09-26 Eddie HungRevert "No need for $__mul anymore?"
2019-09-26 Eddie HungOnly wreduce on t:$add
2019-09-25 Eddie HungRemove _TECHMAP_CELLTYPE_ check since all $mul
2019-09-25 Eddie HungMerge pull request #1401 from SergeyDegtyar/SergeyDegty...
2019-09-25 Eddie HungNo need for $__mul anymore?
2019-09-25 Eddie HungCall 'wreduce' after mul2dsp to avoid unextend()
2019-09-25 Eddie HungOops. Actually use __NAME__ in ABC_DSP48E1 macro
2019-09-24 Eddie HungAdd (* techmap_autopurge *) to abc_unmap.v too
2019-09-24 Eddie HungAdd techmap_autopurge to outputs in abc_map.v too
2019-09-24 Eddie HungRevert "Add a xilinx_finalise pass"
2019-09-24 Eddie HungRevert "Remove (* techmap_autopurge *) from abc_unmap...
2019-09-24 Eddie HungRevert "Vivado does not like zero width port connections"
2019-09-24 Eddie HungVivado does not like zero width port connections
2019-09-24 Eddie HungRemove (* techmap_autopurge *) from abc_unmap.v since...
2019-09-24 Eddie HungAdd a xilinx_finalise pass
2019-09-23 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-09-20 Eddie HungGrammar
2019-09-20 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
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