2020-01-02 |
Eddie Hung | Update comments |
tree | commitdiff |
2020-01-02 |
Eddie Hung | abc9 -keepff -> -dff; refactor dff operations |
tree | commitdiff |
2020-01-01 |
Eddie Hung | Clamp -46ps for FDPE* too |
tree | commitdiff |
2020-01-01 |
Eddie Hung | Restore abc9 -keepff |
tree | commitdiff |
2020-01-01 |
Eddie Hung | Re-arrange FD order |
tree | commitdiff |
2020-01-01 |
Eddie Hung | Missing character |
tree | commitdiff |
2020-01-01 |
Eddie Hung | Cleanup xilinx boxes |
tree | commitdiff |
2020-01-01 |
Eddie Hung | Cleanup ice40 boxes |
tree | commitdiff |
2020-01-01 |
Eddie Hung | Cleanup ecp5 boxes |
tree | commitdiff |
2019-12-31 |
Eddie Hung | Update abc9_xc7.box comments |
tree | commitdiff |
2019-12-31 |
Eddie Hung | FDCE ports to be alphabetical |
tree | commitdiff |
2019-12-31 |
Eddie Hung | Fix attributes on $__ABC9_ASYNC[01] whitebox |
tree | commitdiff |
2019-12-31 |
Eddie Hung | Fix incorrect $__ABC9_ASYNC[01] box |
tree | commitdiff |
2019-12-30 |
Eddie Hung | Do not offset FD* box timings due to -46ps Tsu |
tree | commitdiff |
2019-12-30 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xaig_dff |
tree | commitdiff |
2019-12-30 |
Eddie Hung | Tidy up abc9_map.v |
tree | commitdiff |
2019-12-30 |
Eddie Hung | Add "synth_xilinx -dff" option, cleanup abc9 |
tree | commitdiff |
2019-12-30 |
Miodrag Milanović | Merge pull request #1589 from YosysHQ/iopad_default |
tree | commitdiff |
2019-12-30 |
Eddie Hung | Merge pull request #1599 from YosysHQ/eddie/retry_1588 |
tree | commitdiff |
2019-12-30 |
Eddie Hung | Merge pull request #1600 from YosysHQ/eddie/cleanup_ecp5 |
tree | commitdiff |
2019-12-28 |
Miodrag Milanovic | Merge remote-tracking branch 'origin/master' into iopad... |
tree | commitdiff |
2019-12-28 |
Eddie Hung | Nitpick cleanup for ecp5 |
tree | commitdiff |
2019-12-25 |
Marcin Kościelnicki | Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen |
tree | commitdiff |
2019-12-23 |
Marcin Kościelnicki | xilinx: Test our DSP48A/DSP48A1 simulation models. |
tree | commitdiff |
2019-12-22 |
Marcin Kościelnicki | xilinx_dsp: Initial DSP48A/DSP48A1 support. |
tree | commitdiff |
2019-12-21 |
Miodrag Milanovic | Addressed review comments |
tree | commitdiff |
2019-12-21 |
Miodrag Milanovic | iopad no op for compatibility with old scripts |
tree | commitdiff |
2019-12-21 |
Miodrag Milanovic | Make iopad option default for all xilinx flows |
tree | commitdiff |
2019-12-20 |
Eddie Hung | Merge pull request #1588 from YosysHQ/eddie/xaiger_cleanup |
tree | commitdiff |
2019-12-20 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xaig_dff |
tree | commitdiff |
2019-12-20 |
Eddie Hung | Add abc9_arrival times for RAM{32,64}M |
tree | commitdiff |
2019-12-20 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xaig_dff |
tree | commitdiff |
2019-12-20 |
Eddie Hung | Add RAM{32,64}M to abc9_map.v |
tree | commitdiff |
2019-12-20 |
Eddie Hung | Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lut |
tree | commitdiff |
2019-12-20 |
Eddie Hung | Merge pull request #1587 from YosysHQ/revert-1558-eddie... |
tree | commitdiff |
2019-12-20 |
Eddie Hung | Revert "Optimise write_xaiger" |
tree | commitdiff |
2019-12-19 |
Eddie Hung | Add RAM{32,64}M to abc9_map.v |
tree | commitdiff |
2019-12-19 |
Eddie Hung | Split into $__ABC9_ASYNC[01], do not add cell->type... |
tree | commitdiff |
2019-12-19 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xaig_dff |
tree | commitdiff |
2019-12-19 |
Eddie Hung | Merge pull request #1581 from YosysHQ/clifford/fix1565 |
tree | commitdiff |
2019-12-19 |
Eddie Hung | Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup |
tree | commitdiff |
2019-12-19 |
Eddie Hung | Merge pull request #1569 from YosysHQ/eddie/fix_1531 |
tree | commitdiff |
2019-12-19 |
Eddie Hung | Merge pull request #1571 from YosysHQ/eddie/fix_1570 |
tree | commitdiff |
2019-12-19 |
Marcin Kościelnicki | xilinx: Add simulation models for remaining CLB primitives. |
tree | commitdiff |
2019-12-19 |
Marcin Kościelnicki | xilinx_dffopt: Keep order of LUT inputs. |
tree | commitdiff |
2019-12-18 |
Eddie Hung | Merge branch 'master' of github.com:YosysHQ/yosys |
tree | commitdiff |
2019-12-18 |
David Shah | Merge pull request #1563 from YosysHQ/dave/async-prld |
tree | commitdiff |
2019-12-18 |
Eddie Hung | Merge pull request #1572 from nakengelhardt/scratchpad_pass |
tree | commitdiff |
2019-12-18 |
Marcin Kościelnicki | xilinx: Add xilinx_dffopt pass (#1557) |
tree | commitdiff |
2019-12-18 |
Marcin Kościelnicki | xilinx: Improve flip-flop handling. |
tree | commitdiff |
2019-12-17 |
Eddie Hung | Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram |
tree | commitdiff |
2019-12-17 |
Eddie Hung | Merge pull request #1521 from dh73/diego/memattr |
tree | commitdiff |
2019-12-16 |
Eddie Hung | Add unconditional match blocks for force RAM |
tree | commitdiff |
2019-12-16 |
Eddie Hung | Update xc7/xcu bram rules |
tree | commitdiff |
2019-12-16 |
Eddie Hung | Merge branch 'diego/memattr' of https://github.com... |
tree | commitdiff |
2019-12-16 |
Eddie Hung | Merge branch 'eddie/xilinx_lutram' of github.com:YosysH... |
tree | commitdiff |
2019-12-16 |
Eddie Hung | Populate DID/DOD even if unused |
tree | commitdiff |
2019-12-16 |
Eddie Hung | Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q |
tree | commitdiff |
2019-12-16 |
Diego H | Removing fixed attribute value to !ramstyle rules |
tree | commitdiff |
2019-12-16 |
Diego H | Merging attribute rules into a single match block;... |
tree | commitdiff |
2019-12-16 |
Eddie Hung | Merge pull request #1575 from rodrigomelo9/master |
tree | commitdiff |
2019-12-16 |
Eddie Hung | Merge pull request #1577 from gromero/for-yosys |
tree | commitdiff |
2019-12-13 |
Diego H | Refactoring memory attribute matching based on IEEE... |
tree | commitdiff |
2019-12-13 |
Eddie Hung | Merge pull request #1533 from dh73/bram_xilinx |
tree | commitdiff |
2019-12-13 |
Eddie Hung | Disable RAM16X1D match rule; carry-over from LUT4 arches |
tree | commitdiff |
2019-12-13 |
Eddie Hung | RAM64M8 to also have [5:0] for address |
tree | commitdiff |
2019-12-13 |
Eddie Hung | Add RAM32X6SDP and RAM64X3SDP modes |
tree | commitdiff |
2019-12-13 |
Eddie Hung | Fix RAM64M model to have 6 bit address bus |
tree | commitdiff |
2019-12-13 |
Eddie Hung | Add memory rules for RAM16X1D, RAM32M, RAM64M |
tree | commitdiff |
2019-12-12 |
Diego H | Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB3... |
tree | commitdiff |
2019-12-12 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xaig_dff |
tree | commitdiff |
2019-12-12 |
Eddie Hung | abc9_map.v: fix Xilinx LUTRAM |
tree | commitdiff |
2019-12-12 |
Eddie Hung | abc9_map.v: fix Xilinx LUTRAM |
tree | commitdiff |
2019-12-12 |
Diego H | Updating RAMB36E1 thresholds. Adding test for both... |
tree | commitdiff |
2019-12-12 |
Diego H | Merge https://github.com/YosysHQ/yosys into bram_xilinx |
tree | commitdiff |
2019-12-11 |
Eddie Hung | Fix bitwidth mismatch; suppresses iverilog warning |
tree | commitdiff |
2019-12-11 |
David Shah | Merge pull request #1564 from ZirconiumX/intel_housekeeping |
tree | commitdiff |
2019-12-10 |
Dan Ravensloft | synth_intel: a10gx -> arria10gx |
tree | commitdiff |
2019-12-10 |
Dan Ravensloft | synth_intel: cyclone10 -> cyclone10lp |
tree | commitdiff |
2019-12-10 |
Eddie Hung | Merge pull request #1545 from YosysHQ/eddie/ice40_wrapc... |
tree | commitdiff |
2019-12-09 |
Eddie Hung | Fix comment |
tree | commitdiff |
2019-12-09 |
Eddie Hung | ice40_opt to restore attributes/name when unwrapping |
tree | commitdiff |
2019-12-09 |
Eddie Hung | Sensitive to direct inst of $__ICE40_CARRY_WRAPPER... |
tree | commitdiff |
2019-12-09 |
Eddie Hung | ice40_wrapcarry to really preserve attributes via ... |
tree | commitdiff |
2019-12-07 |
David Shah | ecp5: Add support for mapping PRLD FFs |
tree | commitdiff |
2019-12-07 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xaig_dff |
tree | commitdiff |
2019-12-07 |
Eddie Hung | techmap/aigmap of whiteboxes to occur before abc9 inste... |
tree | commitdiff |
2019-12-07 |
Eddie Hung | Remove creation of $abc9_control_wire |
tree | commitdiff |
2019-12-06 |
Eddie Hung | abc9 to use mergeability class to differentiate sync... |
tree | commitdiff |
2019-12-06 |
Eddie Hung | Remove clkpart |
tree | commitdiff |
2019-12-05 |
Eddie Hung | Revert "Special abc9_clock wire to contain only clock... |
tree | commitdiff |
2019-12-05 |
Clifford Wolf | Merge pull request #1551 from whitequark/manual-cell... |
tree | commitdiff |
2019-12-05 |
Eddie Hung | Missing wire declaration |
tree | commitdiff |
2019-12-05 |
Eddie Hung | abc9_map.v to transform INIT=1 to INIT=0 |
tree | commitdiff |
2019-12-05 |
Eddie Hung | Oh deary me |
tree | commitdiff |
2019-12-05 |
Eddie Hung | output reg Q -> output Q to suppress warning |
tree | commitdiff |
2019-12-05 |
Eddie Hung | abc9_map.v to do `zinit' and make INIT = 1'b0 |
tree | commitdiff |
2019-12-04 |
Marcin Kościelnicki | xilinx: Add tristate buffer mapping. (#1528) |
tree | commitdiff |
2019-12-04 |
Marcin Kościelnicki | xilinx: Add models for LUTRAM cells. (#1537) |
tree | commitdiff |
2019-12-04 |
Eddie Hung | Add abc9_init wire, attach to abc9_flop cell |
tree | commitdiff |
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