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xilinx: Add models for LUTRAM cells. (#1537)
[yosys.git] / tests / arch / gowin /
2019-12-03 Clifford WolfMerge pull request #1524 from pepijndevos/gowindffinit tree | commitdiff
2019-12-03 Pepijn de Vosupdate test tree | commitdiff
2019-12-03 Pepijn de VosUse -match-init to not synth contradicting init values tree | commitdiff
2019-11-27 Clifford WolfMerge pull request #1501 from YosysHQ/dave/mem_copy_attr tree | commitdiff
2019-11-25 Pepijn de Vosattempt to fix formatting tree | commitdiff
2019-11-25 Pepijn de Vosgowin: add and test dff init values tree | commitdiff
2019-11-22 Clifford WolfMerge pull request #1511 from YosysHQ/dave/always tree | commitdiff
2019-11-22 Marcin Kościelnickigowin: Remove show command from tests. tree | commitdiff
2019-11-19 Clifford WolfMerge pull request #1449 from pepijndevos/gowin tree | commitdiff
2019-11-16 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ... tree | commitdiff
2019-11-11 Pepijn de Vosfix fsm test with proper clock enable polarity tree | commitdiff
2019-11-11 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ... tree | commitdiff
2019-11-06 Pepijn de Vosfix wide luts tree | commitdiff
2019-10-30 Pepijn de Vosdon't cound exact luts in big muxes; futile and fragile tree | commitdiff
2019-10-28 Pepijn de Vosadd tristate buffer and test tree | commitdiff
2019-10-28 Pepijn de Vosdo not use wide luts in testcase tree | commitdiff
2019-10-24 Pepijn de VosALU sim tweaks tree | commitdiff
2019-10-21 Pepijn de VosAdd some tests tree | commitdiff