sv: support declaration in generate for initialization
[yosys.git] / tests / bram /
2021-03-11 whitequarkMerge pull request #2642 from whitequark/cxxrtl-noproc...
2021-03-09 whitequarkMerge pull request #2643 from zachjs/fix-param-no-defau...
2021-03-08 Marcelina Koƛcielnickatests/bram: Do not generate write address collisions.
2016-11-01 Clifford WolfAdded support for (single-clock) transparent memories...
2016-10-11 Clifford WolfFixed "make test" for git head of iverilog
2016-09-23 Clifford WolfMerge branch 'master' of https://github.com/brouhaha...
2016-09-22 Eric SmithAdd optional SEED=n command line option to Makefile...
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2015-12-07 Clifford WolfMerge pull request #108 from cseed/master
2015-08-22 Clifford WolfSwitched to Python 3
2015-06-08 luke whittlesey$mem cell in verilog backend : grouped writes by clock
2015-06-04 luke whittleseyBug fix in $mem verilog backend + changed tests/bram...
2015-05-11 Clifford Wolfchanged file() to open() in python scripts
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-01-18 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-01-18 Clifford WolfRefactoring of memory_bram and xilinx brams
2015-01-04 Clifford WolfAdded memory_bram "shuffle_enable" feature
2015-01-03 Clifford WolfAdded "memory -bram"
2015-01-03 Clifford WolfAdded memory_bram 'or_next_if_better' feature
2015-01-03 Clifford Wolfmemory_bram transp support
2015-01-03 Clifford WolfProgress in memory_bram
2015-01-02 Clifford WolfAdded proper clkpol support to memory_bram
2015-01-02 Clifford WolfFixes and improvements in bram test
2015-01-02 Clifford WolfProgress in bram testbench
2015-01-02 Clifford WolfProgress in memory_bram
2015-01-01 Clifford WolfProgress in memory_bram
2015-01-01 Clifford WolfProgress in bram testbench
2015-01-01 Clifford WolfBram testbench (incomplete)