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[gem5.git] / tests / configs / pc-simple-timing-ruby.py

2015-09-30	Mitch Hayenga	isa,cpu: Add support for FS SMT Interrupts	blob \| commitdiff \| raw
2014-11-06	Nilay Vaish	ruby: interface with classic memory controller	blob \| commitdiff \| raw \| diff to current
2014-11-06	Nilay Vaish	ruby: single physical memory in fs mode	blob \| commitdiff \| raw \| diff to current
2014-03-20	Nilay Vaish	config: ruby: rename _cpu_ruby_ports to _cpu_ports	blob \| commitdiff \| raw \| diff to current
2014-03-20	Nilay Vaish	config: remove ruby_fs.py	blob \| commitdiff \| raw \| diff to current
2014-02-24	Nilay Vaish	ruby: route all packets through ruby port	blob \| commitdiff \| raw \| diff to current
2013-08-19	Andreas Hansson	mem: Change AbstractMemory defaults to match the common...	blob \| commitdiff \| raw \| diff to current
2013-08-19	Akash Bagdia	power: Add voltage domains to the clock domains	blob \| commitdiff \| raw \| diff to current
2013-08-19	Andreas Hansson	config: Move the memory instantiation outside FSConfig	blob \| commitdiff \| raw \| diff to current
2013-07-02	Nilay Vaish	regressions: update a couple of configs	blob \| commitdiff \| raw \| diff to current
2013-06-27	Akash Bagdia	sim: Add the notion of clock domains to all ClockedObjects	blob \| commitdiff \| raw \| diff to current
2013-05-30	Andreas Hansson	mem: More descriptive DRAM config names	blob \| commitdiff \| raw \| diff to current
2013-04-22	Andreas Hansson	config: Add a mem-type config option to se/fs scripts	blob \| commitdiff \| raw \| diff to current
2013-03-07	Nilay Vaish	ruby: remove the functional copy of memory in se mode	blob \| commitdiff \| raw \| diff to current
2012-07-21	Andreas Hansson	Regression: Fix topologies path in failing pc-simple...	blob \| commitdiff \| raw \| diff to current
2012-07-11	Brad Beckmann	regress: ruby stat additions and config changes	blob \| commitdiff \| raw \| diff to current
2012-04-26	Nilay Vaish	Regression: Add a test for x86 timing full system ruby...	blob \| commitdiff \| raw \| diff to current

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