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[gem5.git] / tests / configs / realview-o3.py

2020-02-26	Bobby R. Bruce	misc: merge branch 'release-staging-v19.0.0.0' into...	blob \| commitdiff \| raw
2020-02-24	Bobby R. Bruce	misc: Merged release-staging-v19.0.0.0 into develop	blob \| commitdiff \| raw
2020-02-18	Gabe Black	tests: Delete authors lists from test files.	blob \| commitdiff \| raw
2019-12-20	Giacomo Travaglini	configs: arm realview(64) regressions using VExpress_GE...	blob \| commitdiff \| raw \| diff to current
2017-10-05	Curtis Dunham	tests: Fix path for module imports in ARM system config...	blob \| commitdiff \| raw \| diff to current
2017-02-14	Wendy Elsasser	mem: Update DRAM configuration names	blob \| commitdiff \| raw \| diff to current
2016-10-14	Andreas Hansson	config: Make configs/common a Python package	blob \| commitdiff \| raw \| diff to current
2014-09-03	Andreas Hansson	tests: Use O3_ARM_v7a config for full-system ARM regres...	blob \| commitdiff \| raw \| diff to current
2013-08-19	Andreas Hansson	config: Move the memory instantiation outside FSConfig	blob \| commitdiff \| raw \| diff to current
2013-01-07	Andreas Sandberg	tests: Create base classes to encapsulate common test...	blob \| commitdiff \| raw \| diff to current
2012-10-26	Andreas Hansson	config: Fix the cache class naming in regression scripts	blob \| commitdiff \| raw \| diff to current
2012-10-25	Andreas Hansson	config: Use shared cache config for regressions	blob \| commitdiff \| raw \| diff to current
2012-10-15	Andreas Hansson	Mem: Use cycles to express cache-related latencies	blob \| commitdiff \| raw \| diff to current
2012-10-15	Andreas Hansson	Regression: Use addTwoLevelCacheHierarchy in configs	blob \| commitdiff \| raw \| diff to current
2012-09-25	Mrinmoy Ghosh	Cache: add a response latency to the caches	blob \| commitdiff \| raw \| diff to current
2012-05-31	Andreas Hansson	Bus: Split the bus into a non-coherent and coherent bus	blob \| commitdiff \| raw \| diff to current
2012-03-09	Ali Saidi	cache: Allow main memory to be at disjoint address...	blob \| commitdiff \| raw \| diff to current
2012-03-02	Andreas Hansson	CPU: Check that the interrupt controller is created...	blob \| commitdiff \| raw \| diff to current
2012-02-13	Andreas Hansson	MEM: Introduce the master/slave port roles in the Pytho...	blob \| commitdiff \| raw \| diff to current
2012-02-01	Gabe Black	Merge ... head, hopefully the last time for this batch.	blob \| commitdiff \| raw \| diff to current
2012-01-31	Gabe Black	Merge with main repository.	blob \| commitdiff \| raw \| diff to current
2012-01-29	Gabe Black	Yet another merge with the main repository.	blob \| commitdiff \| raw \| diff to current
2012-01-28	Gabe Black	SE/FS: Make SE vs. FS mode a runtime parameter.	blob \| commitdiff \| raw \| diff to current
2012-01-28	Gabe Black	Merge with the main repo.	blob \| commitdiff \| raw \| diff to current
2012-01-17	Andreas Hansson	MEM: Make the bus bridge unidirectional and fixed addre...	blob \| commitdiff \| raw \| diff to current
2012-01-07	Gabe Black	Merge with the main repository again.	blob \| commitdiff \| raw \| diff to current
2011-12-01	Chander Sudanthi	O3: Remove hardcoded tgts_per_mshr in O3CPU.py.	blob \| commitdiff \| raw \| diff to current
2011-08-19	Ali Saidi	ARM: Add some MP regressions and clean up the disk...	blob \| commitdiff \| raw \| diff to current
2011-03-18	Ali Saidi	Automated merge with ssh://hg@repo.m5sim.org/m5	blob \| commitdiff \| raw \| diff to current
2011-03-18	Ali Saidi	ARM: Update stats for the previous changes and add...	blob \| commitdiff \| raw \| diff to current

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