git.libre-soc.org Git - gem5.git/history - tests/configs/tgen-simple-dram.py

2013-08-19	Akash Bagdia	power: Add voltage domains to the clock domains	blob \| commitdiff \| raw
2013-06-27	Akash Bagdia	sim: Add the notion of clock domains to all ClockedObjects	blob \| commitdiff \| raw \| diff to current
2013-06-27	Akash Bagdia	config: Add a system clock command-line option	blob \| commitdiff \| raw \| diff to current
2013-06-27	Akash Bagdia	config: Remove redundant explicit setting of default...	blob \| commitdiff \| raw \| diff to current
2013-05-30	Andreas Hansson	mem: More descriptive DRAM config names	blob \| commitdiff \| raw \| diff to current
2013-01-31	Andreas Hansson	mem: Add DDR3 and LPDDR2 DRAM controller configurations	blob \| commitdiff \| raw \| diff to current
2013-01-07	Andreas Hansson	cpu: Add support for protobuf input for the trace generator	blob \| commitdiff \| raw \| diff to current
2012-09-21	Andreas Hansson	SimpleDRAM: A basic SimpleDRAM regression	blob \| commitdiff \| raw \| diff to current