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mem: Allow read-only caches and check compliance
[gem5.git] / tests / configs / tsunami-o3-dual.py
2013-08-19 Andreas Hanssonconfig: Move the memory instantiation outside FSConfig blob | commitdiff | raw
2013-01-07 Andreas Sandbergtests: Create base classes to encapsulate common test... blob | commitdiff | raw | diff to current
2012-10-26 Andreas Hanssonconfig: Fix the cache class naming in regression scripts blob | commitdiff | raw | diff to current
2012-10-25 Andreas Hanssonconfig: Use shared cache config for regressions blob | commitdiff | raw | diff to current
2012-10-15 Andreas HanssonMem: Use cycles to express cache-related latencies blob | commitdiff | raw | diff to current
2012-09-25 Mrinmoy GhoshCache: add a response latency to the caches blob | commitdiff | raw | diff to current
2012-05-31 Andreas HanssonBus: Split the bus into a non-coherent and coherent bus blob | commitdiff | raw | diff to current
2012-03-09 Ali Saidicache: Allow main memory to be at disjoint address... blob | commitdiff | raw | diff to current
2012-03-02 Andreas HanssonCPU: Check that the interrupt controller is created... blob | commitdiff | raw | diff to current
2012-02-13 Andreas HanssonMEM: Introduce the master/slave port roles in the Pytho... blob | commitdiff | raw | diff to current
2012-02-12 Dam Sunwoomem: fix cache stats to use request ids correctly blob | commitdiff | raw | diff to current
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch. blob | commitdiff | raw | diff to current
2012-01-31 Gabe BlackMerge with main repository. blob | commitdiff | raw | diff to current
2012-01-29 Gabe BlackYet another merge with the main repository. blob | commitdiff | raw | diff to current
2012-01-28 Gabe BlackSE/FS: Make SE vs. FS mode a runtime parameter. blob | commitdiff | raw | diff to current
2012-01-28 Gabe BlackMerge with the main repo. blob | commitdiff | raw | diff to current
2012-01-17 Andreas HanssonMEM: Make the bus bridge unidirectional and fixed addre... blob | commitdiff | raw | diff to current
2012-01-07 Gabe BlackMerge with the main repository again. blob | commitdiff | raw | diff to current
2011-12-01 Chander SudanthiO3: Remove hardcoded tgts_per_mshr in O3CPU.py. blob | commitdiff | raw | diff to current
2011-03-18 Ali SaidiAutomated merge with ssh://hg@repo.m5sim.org/m5 blob | commitdiff | raw | diff to current
2011-03-18 Ali SaidiMem: Fix issue with dirty block being lost when entire... blob | commitdiff | raw | diff to current
2011-02-04 Gabe BlackConfig: Keep track of uncached and cached ports separately. blob | commitdiff | raw | diff to current
2010-02-23 Lisa Hsucache: Make caches sharing aware and add occupancy... blob | commitdiff | raw | diff to current
2010-01-19 Derek Howermerge blob | commitdiff | raw | diff to current
2009-09-22 Nathan Binkertpython: Move more code into m5.util allow SCons to... blob | commitdiff | raw | diff to current
2008-07-16 Steve Reinhardtmem: use single BadAddr responder per system. blob | commitdiff | raw | diff to current
2009-04-06 Gabe BlackMerge ARM into the head. ARM will compile but may not... blob | commitdiff | raw | diff to current
2008-10-20 Ali SaidiRegression: Add single and dual boot O3 regressions... blob | commitdiff | raw | diff to current