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Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)
[yosys.git]
/
tests
/
hana
/
2013-01-05
Clifford Wolf
added more .gitignore files (make test)
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2013-01-05
Clifford Wolf
initial import
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projects / yosys.git / history