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tests: read +/xilinx/cell_sim.v before xilinx_dsp test
[yosys.git]
/
tests
/
proc
/
2020-01-29
Claire Wolf
Merge branch 'vector_fix' of https://github.com/Kmanfi...
tree
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commitdiff
2019-09-27
Aman Goel
Merge pull request #7 from YosysHQ/master
tree
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commitdiff
2019-09-04
Pepijn de Vos
Merge remote-tracking branch 'diego/gowin'
tree
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commitdiff
2019-08-30
David Shah
Merge branch 'master' into xc7dsp
tree
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commitdiff
2019-08-26
Clifford Wolf
Merge tag 'yosys-0.9'
tree
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commitdiff
2019-08-25
Clifford Wolf
Merge pull request #1112 from acw1251/pyosys_sigsig_issue
tree
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commitdiff
2019-08-23
Eddie Hung
Merge remote-tracking branch 'origin/master' into mwk...
tree
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commitdiff
2019-08-22
Clifford Wolf
Merge pull request #1289 from mmicko/anlogic_fixes
tree
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commitdiff
2019-08-22
Clifford Wolf
Merge pull request #1281 from mmicko/efinix
tree
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commitdiff
2019-08-21
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
tree
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commitdiff
2019-08-20
Eddie Hung
Merge pull request #1209 from YosysHQ/eddie/synth_xilinx
tree
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commitdiff
2019-08-20
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
tree
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commitdiff
2019-08-20
Eddie Hung
Merge pull request #1304 from YosysHQ/eddie/abc9_refactor
tree
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commitdiff
2019-08-20
Clifford Wolf
Merge branch 'master' into clifford/pmgen
tree
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commitdiff
2019-08-20
Clifford Wolf
Merge pull request #1308 from jakobwenzel/real_params
tree
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commitdiff
2019-08-20
whitequark
Merge pull request #1309 from whitequark/proc_clean...
tree
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commitdiff
2019-08-19
whitequark
proc_clean: fix order of switch insertion.
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commitdiff