xilinx: Add models for LUTRAM cells. (#1537)
[yosys.git] / tests / sat /
2019-10-08 Eddie HungRevert "Add test that is expecting to fail"
2019-10-08 Eddie HungMerge pull request #1432 from YosysHQ/eddie/fix1427
2019-10-03 Eddie HungMerge branch 'eddie/fix_sat_init' into eddie/fix1427
2019-10-02 Eddie HungAdd test that is expecting to fail
2019-09-27 Aman GoelMerge pull request #7 from YosysHQ/master
2019-09-04 Pepijn de VosMerge remote-tracking branch 'diego/gowin'
2019-08-30 Eddie HungMerge branch 'xc7dsp' of github.com:YosysHQ/yosys into...
2019-08-30 David ShahMerge branch 'master' into xc7dsp
2019-08-29 SergeyMerge pull request #3 from YosysHQ/Sergey/tests_ice40
2019-08-28 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_...
2019-08-28 Eddie HungMerge remote-tracking branch 'origin/clifford/async2syn...
2019-08-28 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-28 David ShahMerge pull request #1332 from YosysHQ/dave/ecp5gsr
2019-08-27 Clifford WolfMerge pull request #1325 from YosysHQ/eddie/sat_init
2019-08-27 Eddie HungRevert to using clean
2019-08-27 Eddie HungRevert "In sat: 'x' in init attr should not override...
2019-08-26 Eddie HungMerge branch 'master' into eddie/xilinx_srl
2019-08-24 Eddie HungWire with init on FF part, 1'bx on non-FF part
2019-08-23 Eddie HungMerge remote-tracking branch 'origin/clifford/pmgen...
2019-08-23 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-23 Eddie HungBlocking assignment
2019-08-22 Eddie HungIn sat: 'x' in init attr should not override constant
2019-08-22 Eddie HungIn sat: 'x' in init attr should not override constant
2019-06-13 Serge BazanskiMerge pull request #829 from abdelrahmanhosny/master
2019-04-30 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-04-30 Benedikt TutzerMerge branch 'master' of https://github.com/YosysHQ...
2019-04-22 Eddie HungMerge remote-tracking branch 'origin/xc7srl' into xc7mux
2019-04-22 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-04-22 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-22 Clifford WolfMerge pull request #905 from christian-krieg/feature...
2019-04-22 Clifford WolfMerge pull request #941 from Wren6991/sim_lib_io_clke
2019-04-22 Clifford WolfMerge branch 'master' of https://github.com/dh73/yosys_...
2019-04-22 Clifford WolfMerge pull request #916 from YosysHQ/map_cells_before_m...
2019-04-22 Clifford WolfMerge pull request #911 from mmicko/gowin-nobram
2019-04-22 Clifford WolfMerge pull request #909 from zachjs/master
2019-04-09 Zachary Snowsupport repeat loops with constant repeat counts outsid...
2017-09-29 Clifford WolfAllow $size and $bits in verilog mode, actually check...
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-07-20 Clifford WolfAdded yet another resource sharing test case
2014-07-05 Clifford Wolfnow ignore init attributes on non-register wires in...
2014-06-12 Clifford WolfAdded read_verilog -sv options, added support for bit...
2014-02-08 Clifford WolfAdded test cases for expose -evert-dff
2014-02-07 Clifford WolfAdded splice command
2014-02-06 Clifford WolfAdded counters sat test case
2014-02-04 Clifford WolfAdded test cases for sat command