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Use mem2reg on memories that only have constant-index write ports
[yosys.git] / tests / sat /
2017-09-29 Clifford WolfAllow $size and $bits in verilog mode, actually check... tree | commitdiff
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... tree | commitdiff
2014-07-20 Clifford WolfAdded yet another resource sharing test case tree | commitdiff
2014-07-05 Clifford Wolfnow ignore init attributes on non-register wires in... tree | commitdiff
2014-06-12 Clifford WolfAdded read_verilog -sv options, added support for bit... tree | commitdiff
2014-02-08 Clifford WolfAdded test cases for expose -evert-dff tree | commitdiff
2014-02-07 Clifford WolfAdded splice command tree | commitdiff
2014-02-06 Clifford WolfAdded counters sat test case tree | commitdiff
2014-02-04 Clifford WolfAdded test cases for sat command tree | commitdiff