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xilinx: Add models for LUTRAM cells. (#1537)
[yosys.git]
/
tests
/
share
/
generate.py
2016-09-23
Clifford Wolf
Merge branch 'master' of https://github.com/brouhaha...
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2016-09-22
Eric Smith
Add optional SEED=n command line option to Makefile...
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2015-12-07
Clifford Wolf
Merge pull request #108 from cseed/master
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2015-08-22
Clifford Wolf
Switched to Python 3
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2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2015-05-11
Clifford Wolf
changed file() to open() in python scripts
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2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2015-03-20
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2015-03-20
Clifford Wolf
fix for python 2.6.6
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-08-03
Clifford Wolf
Added "wreduce" to some of the standard test benches
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2014-07-21
Clifford Wolf
Wider range of cell types supported in "share" pass
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2014-07-20
Clifford Wolf
Supercell creation for $div/$mod worked all along,...
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2014-07-20
Clifford Wolf
Improved tests/share/generate.py
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2014-07-20
Clifford Wolf
Added "miter -equiv -flatten"
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2014-07-20
Clifford Wolf
Added tests/share for testing "share" supercell creation
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