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Added tests for attributes
[yosys.git]
/
tests
/
simple
/
specify.v
2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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2018-08-15
Clifford Wolf
Merge pull request #513 from udif/pr_reg_wire_error
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2018-03-27
Clifford Wolf
Fix tests/simple/specify.v
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2018-03-27
Udi Finkelstein
First draft of Verilog parser support for specify block...
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