Merge pull request #722 from whitequark/rename_src
[yosys.git] / tests / simple /
2018-10-21 rafaeltpMerge pull request #1 from YosysHQ/master
2018-10-19 Clifford WolfMerge pull request #671 from rafaeltp/master
2018-10-19 Clifford WolfMerge pull request #670 from rubund/feature/basic_svint...
2018-10-18 Ruben UndheimBasic test for checking correct synthesis of SystemVeri...
2018-10-18 Clifford WolfMerge pull request #659 from rubund/sv_interfaces
2018-10-12 Ruben UndheimSupport for 'modports' for System Verilog interfaces
2018-10-12 Ruben UndheimSynthesis support for SystemVerilog interfaces
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-15 Clifford WolfMerge pull request #513 from udif/pr_reg_wire_error
2018-06-05 Udi Finkelsteinreg_wire_error test needs the -sv flag so it is run...
2018-03-27 Clifford WolfFix tests/simple/specify.v
2018-03-27 Udi FinkelsteinFirst draft of Verilog parser support for specify block...
2018-03-11 Udi FinkelsteinThis PR should be the base for discussion, do not merge...
2017-09-29 Clifford WolfAllow $size and $bits in verilog mode, actually check...
2017-09-29 Clifford WolfMerge pull request #425 from udif/udif_dollar_bits
2017-09-26 Udi Finkelstein$size() now works correctly for all cases!
2017-09-26 Udi Finkelstein$size() seems to work now with or without the optional...
2017-09-26 Udi FinkelsteinAdded $bits() for memories as well.
2017-09-26 Udi Finkelstein$size() now works with memories as well!
2017-09-26 Udi FinkelsteinAdd $size() function. At the moment it works only on...
2017-04-12 Larry DoolittleSquelch trailing whitespace
2017-01-05 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-01-04 Clifford WolfFixed typo in tests/simple/arraycells.v
2016-11-15 Clifford WolfAdded support for hierarchical defparams
2016-09-23 Clifford WolfMerge branch 'master' of https://github.com/brouhaha...
2016-09-22 Eric SmithAdd optional SEED=n command line option to Makefile...
2016-08-22 Clifford WolfFixed bug with memories that do not have a down-to...
2016-08-21 Clifford WolfAdded another mem2reg test case
2016-08-21 Clifford WolfAnother bugfix in mem2reg code
2016-07-08 Clifford WolfFixed mem assignment in left-hand-side concatenation
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-06-17 Clifford WolfFixed init issue in mem2reg_test2 test case
2016-05-29 Clifford WolfAdded opt_expr support for div/mod by power-of-two
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-21 Clifford WolfBugfix and improvements in memory_share
2015-12-07 Clifford WolfMerge pull request #108 from cseed/master
2015-11-30 Clifford WolfAdded tests/simple/graphtest.v
2015-11-12 Clifford WolfMore bugfixes in handling of parameters in tasks and...
2015-11-11 Clifford WolfFixed handling of parameters and localparams in functions
2015-10-31 Clifford WolfBugfix in memory_dff
2015-10-31 Clifford WolfImprovements in wreduce
2015-08-14 Larry DoolittleAnother block of spelling fixes
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-02-14 Clifford WolfVarious fixes for memories with offsets
2015-02-14 Clifford WolfAdded $meminit support to "memory" command
2015-02-14 Clifford WolfAdded $meminit test case
2015-01-18 Clifford Wolfimprovements in muxtree/select_leaves test
2015-01-18 Clifford WolfImprovements in opt_muxtree
2014-10-27 Clifford WolfAdded support for task and function args in parentheses
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-08-12 Clifford WolfAdded multi-dim memory test (requires iverilog git...
2014-08-05 Clifford WolfImproved scope resolution of local regs in Verilog...
2014-08-05 Clifford WolfFixed AST handling of variables declared inside a funct...
2014-07-30 Clifford WolfAdded "make -j{N}" support to "make test"
2014-07-28 Clifford WolfAdded support for "upto" wires to Verilog front- and...
2014-07-25 Clifford WolfRenamed some of the test cases in tests/simple to avoid...
2014-07-17 Clifford WolfImplemented dynamic bit-/part-select for memory writes
2014-07-17 Clifford WolfAdded support for bit/part select to mem2reg rewriter
2014-07-17 Clifford WolfAdded support for constant bit- or part-select for...
2014-07-16 Clifford WolfAdded note to "make test": use git checkout of iverilog
2014-07-02 Clifford Wolffixed parsing of constant with comment between size...
2014-06-25 Clifford WolfFixed handling of mixed real/int ternary expressions
2014-06-21 Clifford WolfLittle steps in realmath test bench
2014-06-17 Clifford WolfAdded test case for AstNode::MEM2REG_FL_CMPLX_LHS
2014-06-15 Clifford WolfRemoved long running tests from tests/simple/realexpr...
2014-06-15 Clifford WolfAdded tests/realmath to "make test"
2014-06-14 Clifford WolfAdded support for math functions
2014-06-14 Clifford WolfAdded realexpr.v test case
2014-06-07 Clifford Wolfadded tests for new verilog features
2014-06-06 Clifford WolfAdded tests/simple/repwhile.v
2014-03-17 Clifford WolfProgress in Verific bindings
2014-02-03 Clifford WolfAdded TRANSPARENT parameter to $memrd (and RD_TRANSPARE...
2014-01-30 Clifford WolfBugfix in name resolution with generate blocks
2014-01-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-02 Clifford WolfAdded correct handling of $memwr priority
2013-12-27 Clifford WolfAdded proper === and !== support in constant expressions
2013-12-18 Clifford WolfAdded multiplier test case from eda playground
2013-12-18 Clifford WolfAdded elsif preproc support
2013-12-18 Clifford WolfAdded support for macro arguments
2013-12-04 Clifford WolfVarious improvements in support for generate statements
2013-12-04 Clifford WolfReplaced RTLIL::Const::str with generic decoder method
2013-12-04 Clifford WolfFix in sincos testbench gen
2013-12-04 Clifford WolfAdded sincos test case
2013-11-24 Clifford WolfImplemented correct handling of signed module parameters
2013-11-24 Clifford WolfAdded modelsim support to autotest
2013-11-20 Clifford WolfAnother name resolution bugfix for generate blocks
2013-11-20 Clifford WolfImplemented indexed part selects
2013-11-20 Clifford WolfImplemented part/bit select on memory read
2013-11-18 Clifford WolfAdded additional mem2reg testcase
2013-11-18 Clifford WolfFixed parsing of default cases when not last case
2013-11-07 Clifford WolfFixed handling of power operator
2013-11-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-11-02 Clifford WolfBehavior should be identical now to rev. 0b4a64ac6adbd6...
2013-11-02 Clifford WolfVarious ast changes for early expression width detectio...
2013-10-24 Clifford WolfAdded support for complex set-reset flip-flops in proc_dff
2013-10-21 Clifford WolfImproved handling of dff with async resets
2013-08-12 Clifford WolfAdded support for "2**n" shifter encoding
2013-08-09 Clifford WolfAdded $div and $mod technology mapping
2013-07-12 Clifford WolfMore fixes in ternary op sign handling
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