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Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)
[yosys.git] / tests / simple /
2014-02-03 Clifford WolfAdded TRANSPARENT parameter to $memrd (and RD_TRANSPARE... tree | commitdiff
2014-01-30 Clifford WolfBugfix in name resolution with generate blocks tree | commitdiff
2014-01-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... tree | commitdiff
2014-01-02 Clifford WolfAdded correct handling of $memwr priority tree | commitdiff
2013-12-27 Clifford WolfAdded proper === and !== support in constant expressions tree | commitdiff
2013-12-18 Clifford WolfAdded multiplier test case from eda playground tree | commitdiff
2013-12-18 Clifford WolfAdded elsif preproc support tree | commitdiff
2013-12-18 Clifford WolfAdded support for macro arguments tree | commitdiff
2013-12-04 Clifford WolfVarious improvements in support for generate statements tree | commitdiff
2013-12-04 Clifford WolfReplaced RTLIL::Const::str with generic decoder method tree | commitdiff
2013-12-04 Clifford WolfFix in sincos testbench gen tree | commitdiff
2013-12-04 Clifford WolfAdded sincos test case tree | commitdiff
2013-11-24 Clifford WolfImplemented correct handling of signed module parameters tree | commitdiff
2013-11-24 Clifford WolfAdded modelsim support to autotest tree | commitdiff
2013-11-20 Clifford WolfAnother name resolution bugfix for generate blocks tree | commitdiff
2013-11-20 Clifford WolfImplemented indexed part selects tree | commitdiff
2013-11-20 Clifford WolfImplemented part/bit select on memory read tree | commitdiff
2013-11-18 Clifford WolfAdded additional mem2reg testcase tree | commitdiff
2013-11-18 Clifford WolfFixed parsing of default cases when not last case tree | commitdiff
2013-11-07 Clifford WolfFixed handling of power operator tree | commitdiff
2013-11-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys tree | commitdiff
2013-11-02 Clifford WolfBehavior should be identical now to rev. 0b4a64ac6adbd6... tree | commitdiff
2013-11-02 Clifford WolfVarious ast changes for early expression width detectio... tree | commitdiff
2013-10-24 Clifford WolfAdded support for complex set-reset flip-flops in proc_dff tree | commitdiff
2013-10-21 Clifford WolfImproved handling of dff with async resets tree | commitdiff
2013-08-12 Clifford WolfAdded support for "2**n" shifter encoding tree | commitdiff
2013-08-09 Clifford WolfAdded $div and $mod technology mapping tree | commitdiff
2013-07-12 Clifford WolfMore fixes in ternary op sign handling tree | commitdiff
2013-07-11 Clifford WolfFixed sign handling in ternary operator tree | commitdiff
2013-07-11 Clifford WolfAnother vloghammer related bugfix tree | commitdiff
2013-07-09 Clifford WolfMore fixes in ast expression sign/width handling tree | commitdiff
2013-07-09 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys tree | commitdiff
2013-07-09 Clifford WolfFixed shift ops with large right hand side tree | commitdiff
2013-07-09 Clifford WolfMajor redesign of expr width/sign detecion (verilog... tree | commitdiff
2013-07-07 Clifford WolfFixed another bug found using vloghammer tree | commitdiff
2013-07-04 Clifford WolfAdded defparam support to Verilog/AST frontend tree | commitdiff
2013-05-16 Clifford WolfMerge branch 'bugfix' tree | commitdiff
2013-04-13 Clifford WolfFixed a bug in AST frontend for cases with non-blocking... tree | commitdiff
2013-03-31 Clifford WolfAdded test cases from 2012 paper on comparison of foss... tree | commitdiff
2013-03-24 Clifford WolfRenamed hansimem.v test case to mem_arst.v tree | commitdiff
2013-03-24 Clifford WolfAdded hansimem testcase (memory with async reset) tree | commitdiff
2013-03-17 Clifford WolfMerge branch 'hansi' tree | commitdiff
2013-03-17 Johann Glaseradded ckeck for Icarus Verilog, otherwise the tests... tree | commitdiff
2013-01-05 Clifford Wolfadded more .gitignore files (make test) tree | commitdiff
2013-01-05 Clifford Wolfinitial import tree | commitdiff