projects
/
yosys.git
/ history
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
first
⋅
prev
⋅
next
Test *.aag too, by using *.aig as reference
[yosys.git]
/
tests
/
simple
/
2018-03-27
Clifford Wolf
Fix tests/simple/specify.v
tree
|
commitdiff
2018-03-27
Udi Finkelstein
First draft of Verilog parser support for specify block...
tree
|
commitdiff
2018-03-11
Udi Finkelstein
This PR should be the base for discussion, do not merge...
tree
|
commitdiff
2017-09-29
Clifford Wolf
Allow $size and $bits in verilog mode, actually check...
tree
|
commitdiff
2017-09-29
Clifford Wolf
Merge pull request #425 from udif/udif_dollar_bits
tree
|
commitdiff
2017-09-26
Udi Finkelstein
$size() now works correctly for all cases!
tree
|
commitdiff
2017-09-26
Udi Finkelstein
$size() seems to work now with or without the optional...
tree
|
commitdiff
2017-09-26
Udi Finkelstein
Added $bits() for memories as well.
tree
|
commitdiff
2017-09-26
Udi Finkelstein
$size() now works with memories as well!
tree
|
commitdiff
2017-09-26
Udi Finkelstein
Add $size() function. At the moment it works only on...
tree
|
commitdiff
2017-04-12
Larry Doolittle
Squelch trailing whitespace
tree
|
commitdiff
2017-01-05
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
tree
|
commitdiff
2017-01-04
Clifford Wolf
Fixed typo in tests/simple/arraycells.v
tree
|
commitdiff
2016-11-15
Clifford Wolf
Added support for hierarchical defparams
tree
|
commitdiff
2016-09-23
Clifford Wolf
Merge branch 'master' of https://github.com/brouhaha...
tree
|
commitdiff
2016-09-22
Eric Smith
Add optional SEED=n command line option to Makefile...
tree
|
commitdiff
2016-08-22
Clifford Wolf
Fixed bug with memories that do not have a down-to...
tree
|
commitdiff
2016-08-21
Clifford Wolf
Added another mem2reg test case
tree
|
commitdiff
2016-08-21
Clifford Wolf
Another bugfix in mem2reg code
tree
|
commitdiff
2016-07-08
Clifford Wolf
Fixed mem assignment in left-hand-side concatenation
tree
|
commitdiff
2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
tree
|
commitdiff
2016-06-17
Clifford Wolf
Fixed init issue in mem2reg_test2 test case
tree
|
commitdiff
2016-05-29
Clifford Wolf
Added opt_expr support for div/mod by power-of-two
tree
|
commitdiff
2016-04-23
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
tree
|
commitdiff
2016-04-21
Clifford Wolf
Bugfix and improvements in memory_share
tree
|
commitdiff
2015-12-07
Clifford Wolf
Merge pull request #108 from cseed/master
tree
|
commitdiff
2015-11-30
Clifford Wolf
Added tests/simple/graphtest.v
tree
|
commitdiff
2015-11-12
Clifford Wolf
More bugfixes in handling of parameters in tasks and...
tree
|
commitdiff
2015-11-11
Clifford Wolf
Fixed handling of parameters and localparams in functions
tree
|
commitdiff
2015-10-31
Clifford Wolf
Bugfix in memory_dff
tree
|
commitdiff
2015-10-31
Clifford Wolf
Improvements in wreduce
tree
|
commitdiff
2015-08-14
Larry Doolittle
Another block of spelling fixes
tree
|
commitdiff
2015-07-02
Clifford Wolf
Fixed trailing whitespaces
tree
|
commitdiff
2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
tree
|
commitdiff
2015-02-14
Clifford Wolf
Various fixes for memories with offsets
tree
|
commitdiff
2015-02-14
Clifford Wolf
Added $meminit support to "memory" command
tree
|
commitdiff
2015-02-14
Clifford Wolf
Added $meminit test case
tree
|
commitdiff
2015-01-18
Clifford Wolf
improvements in muxtree/select_leaves test
tree
|
commitdiff
2015-01-18
Clifford Wolf
Improvements in opt_muxtree
tree
|
commitdiff
2014-10-27
Clifford Wolf
Added support for task and function args in parentheses
tree
|
commitdiff
2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
tree
|
commitdiff
2014-08-12
Clifford Wolf
Added multi-dim memory test (requires iverilog git...
tree
|
commitdiff
2014-08-05
Clifford Wolf
Improved scope resolution of local regs in Verilog...
tree
|
commitdiff
2014-08-05
Clifford Wolf
Fixed AST handling of variables declared inside a funct...
tree
|
commitdiff
2014-07-30
Clifford Wolf
Added "make -j{N}" support to "make test"
tree
|
commitdiff
2014-07-28
Clifford Wolf
Added support for "upto" wires to Verilog front- and...
tree
|
commitdiff
2014-07-25
Clifford Wolf
Renamed some of the test cases in tests/simple to avoid...
tree
|
commitdiff
2014-07-17
Clifford Wolf
Implemented dynamic bit-/part-select for memory writes
tree
|
commitdiff
2014-07-17
Clifford Wolf
Added support for bit/part select to mem2reg rewriter
tree
|
commitdiff
2014-07-17
Clifford Wolf
Added support for constant bit- or part-select for...
tree
|
commitdiff
2014-07-16
Clifford Wolf
Added note to "make test": use git checkout of iverilog
tree
|
commitdiff
2014-07-02
Clifford Wolf
fixed parsing of constant with comment between size...
tree
|
commitdiff
2014-06-25
Clifford Wolf
Fixed handling of mixed real/int ternary expressions
tree
|
commitdiff
2014-06-21
Clifford Wolf
Little steps in realmath test bench
tree
|
commitdiff
2014-06-17
Clifford Wolf
Added test case for AstNode::MEM2REG_FL_CMPLX_LHS
tree
|
commitdiff
2014-06-15
Clifford Wolf
Removed long running tests from tests/simple/realexpr...
tree
|
commitdiff
2014-06-15
Clifford Wolf
Added tests/realmath to "make test"
tree
|
commitdiff
2014-06-14
Clifford Wolf
Added support for math functions
tree
|
commitdiff
2014-06-14
Clifford Wolf
Added realexpr.v test case
tree
|
commitdiff
2014-06-07
Clifford Wolf
added tests for new verilog features
tree
|
commitdiff
2014-06-06
Clifford Wolf
Added tests/simple/repwhile.v
tree
|
commitdiff
2014-03-17
Clifford Wolf
Progress in Verific bindings
tree
|
commitdiff
2014-02-03
Clifford Wolf
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARE...
tree
|
commitdiff
2014-01-30
Clifford Wolf
Bugfix in name resolution with generate blocks
tree
|
commitdiff
2014-01-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
tree
|
commitdiff
2014-01-02
Clifford Wolf
Added correct handling of $memwr priority
tree
|
commitdiff
2013-12-27
Clifford Wolf
Added proper === and !== support in constant expressions
tree
|
commitdiff
2013-12-18
Clifford Wolf
Added multiplier test case from eda playground
tree
|
commitdiff
2013-12-18
Clifford Wolf
Added elsif preproc support
tree
|
commitdiff
2013-12-18
Clifford Wolf
Added support for macro arguments
tree
|
commitdiff
2013-12-04
Clifford Wolf
Various improvements in support for generate statements
tree
|
commitdiff
2013-12-04
Clifford Wolf
Replaced RTLIL::Const::str with generic decoder method
tree
|
commitdiff
2013-12-04
Clifford Wolf
Fix in sincos testbench gen
tree
|
commitdiff
2013-12-04
Clifford Wolf
Added sincos test case
tree
|
commitdiff
2013-11-24
Clifford Wolf
Implemented correct handling of signed module parameters
tree
|
commitdiff
2013-11-24
Clifford Wolf
Added modelsim support to autotest
tree
|
commitdiff
2013-11-20
Clifford Wolf
Another name resolution bugfix for generate blocks
tree
|
commitdiff
2013-11-20
Clifford Wolf
Implemented indexed part selects
tree
|
commitdiff
2013-11-20
Clifford Wolf
Implemented part/bit select on memory read
tree
|
commitdiff
2013-11-18
Clifford Wolf
Added additional mem2reg testcase
tree
|
commitdiff
2013-11-18
Clifford Wolf
Fixed parsing of default cases when not last case
tree
|
commitdiff
2013-11-07
Clifford Wolf
Fixed handling of power operator
tree
|
commitdiff
2013-11-03
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
tree
|
commitdiff
2013-11-02
Clifford Wolf
Behavior should be identical now to rev. 0b4a64ac6adbd6...
tree
|
commitdiff
2013-11-02
Clifford Wolf
Various ast changes for early expression width detectio...
tree
|
commitdiff
2013-10-24
Clifford Wolf
Added support for complex set-reset flip-flops in proc_dff
tree
|
commitdiff
2013-10-21
Clifford Wolf
Improved handling of dff with async resets
tree
|
commitdiff
2013-08-12
Clifford Wolf
Added support for "2**n" shifter encoding
tree
|
commitdiff
2013-08-09
Clifford Wolf
Added $div and $mod technology mapping
tree
|
commitdiff
2013-07-12
Clifford Wolf
More fixes in ternary op sign handling
tree
|
commitdiff
2013-07-11
Clifford Wolf
Fixed sign handling in ternary operator
tree
|
commitdiff
2013-07-11
Clifford Wolf
Another vloghammer related bugfix
tree
|
commitdiff
2013-07-09
Clifford Wolf
More fixes in ast expression sign/width handling
tree
|
commitdiff
2013-07-09
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
tree
|
commitdiff
2013-07-09
Clifford Wolf
Fixed shift ops with large right hand side
tree
|
commitdiff
2013-07-09
Clifford Wolf
Major redesign of expr width/sign detecion (verilog...
tree
|
commitdiff
2013-07-07
Clifford Wolf
Fixed another bug found using vloghammer
tree
|
commitdiff
2013-07-04
Clifford Wolf
Added defparam support to Verilog/AST frontend
tree
|
commitdiff
2013-05-16
Clifford Wolf
Merge branch 'bugfix'
tree
|
commitdiff
2013-04-13
Clifford Wolf
Fixed a bug in AST frontend for cases with non-blocking...
tree
|
commitdiff
next