Added additional mem2reg testcase
[yosys.git] / tests / simple /
2013-11-18 Clifford WolfAdded additional mem2reg testcase
2013-11-18 Clifford WolfFixed parsing of default cases when not last case
2013-11-07 Clifford WolfFixed handling of power operator
2013-11-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-11-02 Clifford WolfBehavior should be identical now to rev. 0b4a64ac6adbd6...
2013-11-02 Clifford WolfVarious ast changes for early expression width detectio...
2013-10-24 Clifford WolfAdded support for complex set-reset flip-flops in proc_dff
2013-10-21 Clifford WolfImproved handling of dff with async resets
2013-08-12 Clifford WolfAdded support for "2**n" shifter encoding
2013-08-09 Clifford WolfAdded $div and $mod technology mapping
2013-07-12 Clifford WolfMore fixes in ternary op sign handling
2013-07-11 Clifford WolfFixed sign handling in ternary operator
2013-07-11 Clifford WolfAnother vloghammer related bugfix
2013-07-09 Clifford WolfMore fixes in ast expression sign/width handling
2013-07-09 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-07-09 Clifford WolfFixed shift ops with large right hand side
2013-07-09 Clifford WolfMajor redesign of expr width/sign detecion (verilog...
2013-07-07 Clifford WolfFixed another bug found using vloghammer
2013-07-04 Clifford WolfAdded defparam support to Verilog/AST frontend
2013-05-16 Clifford WolfMerge branch 'bugfix'
2013-04-13 Clifford WolfFixed a bug in AST frontend for cases with non-blocking...
2013-03-31 Clifford WolfAdded test cases from 2012 paper on comparison of foss...
2013-03-24 Clifford WolfRenamed hansimem.v test case to mem_arst.v
2013-03-24 Clifford WolfAdded hansimem testcase (memory with async reset)
2013-03-17 Clifford WolfMerge branch 'hansi'
2013-03-17 Johann Glaseradded ckeck for Icarus Verilog, otherwise the tests...
2013-01-05 Clifford Wolfadded more .gitignore files (make test)
2013-01-05 Clifford Wolfinitial import