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Use mem2reg on memories that only have constant-index write ports
[yosys.git] / tests / sva /
2019-01-02 Clifford WolfMerge pull request #755 from Icenowy/anlogic-dram-init tree | commitdiff
2019-01-02 Clifford WolfMerge pull request #750 from Icenowy/anlogic-ff-init tree | commitdiff
2018-12-31 Clifford WolfMerge pull request #766 from Icenowy/anlogic-latches tree | commitdiff
2018-12-29 Larry DoolittleSquelch a little more trailing whitespace tree | commitdiff
2018-02-28 Clifford WolfMerge branch 'verificsva-ng' tree | commitdiff
2018-02-27 Clifford WolfMajor redesign of Verific SVA importer tree | commitdiff
2018-02-21 Clifford WolfAdd support for SVA throughout via Verific tree | commitdiff
2018-02-18 Clifford WolfAdd support for SVA sequence concatenation ranges via... tree | commitdiff
2018-02-18 Clifford WolfAdd support for SVA until statements via Verific tree | commitdiff
2018-02-16 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys tree | commitdiff
2018-02-15 Clifford WolfFix verific PRIM_SVA_AT handling in properties with... tree | commitdiff
2017-11-09 dh73Merge https://github.com/cliffordwolf/yosys tree | commitdiff
2017-10-20 Clifford WolfRemove PSL example from tests/sva/ tree | commitdiff
2017-07-28 Clifford WolfAdd simple VHDL+PSL example tree | commitdiff
2017-07-27 Clifford WolfImprove Verific SVA importer tree | commitdiff
2017-07-27 Clifford WolfAdd counter.sv SVA test tree | commitdiff
2017-07-27 Clifford WolfImprove SVA tests, add Makefile and scripts tree | commitdiff
2017-07-22 Clifford WolfAdd more SVA test cases for future Verific work tree | commitdiff
2017-07-22 Clifford WolfAdd some simple SVA test cases for future Verific work tree | commitdiff